Multi-Stage Flash Memory Decoding for Lower Read Latency

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Solution Overview

Problem

Flash memory introduces data errors due to manufacturing variations and aging, which existing error correcting codes like LDPC codes attempt to address but at the cost of adding latency to read operations.

Innovation Solution

A method that selects a preliminary read-level voltage based on a decoding success indicator for a preliminary hard decoding operation, and if unsuccessful, executes a multi-stage decoding operation using a sequence of read-level voltages, allowing for efficient error recovery without progressing through all stages if previous decoding was successful.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If LDPC codes are used for error correction, then error correcting capability is improved, but read operation latency increases

Engineering Contradiction:
Improveerror correcting capabilityVSAvoidread operation latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs a preliminary hard decoding operation before the full multi-stage LDPC decoding process. This preliminary action uses a simplified decoding approach that can quickly determine if error correction is needed, avoiding the latency of complete LDPC decoding when errors are absent or minimal.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The decoding process is segmented into multiple stages: a preliminary hard decoding stage followed by conditional multi-stage soft decoding stages. This segmentation allows the system to apply the full complexity of LDPC decoding only when necessary, reducing average latency while maintaining error correction capability.

Inventive Principle:
Principle #1Segmentation

2Reliability

If multi-stage decoding operation is executed for all reads, then error recovery efficiency is improved, but latency increases due to unnecessary decoding stages

Engineering Contradiction:
Improveerror recovery efficiencyVSAvoiddecoding latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies partial action by executing only the preliminary hard decoding stage for all reads, and then applying the full multi-stage soft decoding only when the preliminary stage indicates decoding failure. This avoids excessive action (running all stages for every read) while ensuring adequate error recovery when needed.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The decoding process is made dynamic by conditionally progressing through decoding stages based on the results of previous stages. The system adapts the decoding depth required for each read operation, transitioning from a static always-full-decoding approach to a dynamic conditional approach that adjusts complexity based on actual error conditions.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11093326B2Dynamic multi-stage decoding
Publication Date: 2021.08.17 SANDISK TECHNOLOGIES LLC
  • US11093326B2 patent drawing
  • US11093326B2 patent drawing
  • US11093326B2 patent drawing

AI summary

Methods and systems for decoding raw data may select a preliminary read-level voltage from a sequence of read-level voltages based on a decoding success indicator and execute a preliminary hard decoding operation to decode raw data read from a plurality of memory cells using the preliminary read-level voltage. If the preliminary hard decoding operation is successful, the decoded data from the hard decoding operation is returned. If the preliminary hard decoding operation is unsuccessful, a multi-stage decoding operation may be executed to decode raw data read from the plurality of memory cells using the sequence of read-level voltages, and returning decoded data from the multi-stage decoding operation upon completion of the multi-stage decoding operation. The decoding success indicator is maintained based on results of the preliminary hard decoding operation or the multi-stage decoding operation.