Flash Memory Test Logic for ECC-Aware Defect Screening
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Solution Overview
Problem
Conventional semiconductor memory test apparatuses incorrectly determine flash memory as defective due to software errors that can be corrected by error correction codes, failing to differentiate between permanent and non-permanent errors.
Innovation Solution
A test apparatus and method that includes a logic comparator, data error count unit, and defect detection unit to compare data strings with anticipated values, counting errors and determining memory defects only when errors exceed correctable limits or occur in regions without error correction codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional test apparatus compares output with anticipated value for each test cycle and determines fail on any mismatch, then measurement precision is improved, but false failure assessment occurs due to correctable software errors
Solution Approach 1:
The patent segments the error evaluation process into two distinct stages: (1) data comparison stage where all mismatches are detected with high precision, and (2) defect determination stage where errors are categorized as correctable or permanent. This segmentation allows the system to maintain measurement precision in detecting all errors while improving reliability by excluding correctable errors from failure determinations.
Solution Approach 2:
The patent introduces an intermediary component (defect detection unit or controller) that acts as a mediator between the data comparison unit and the failure determination logic. This intermediary counts mismatched data sets, compares the count against predetermined thresholds, and only triggers failure determination when the threshold is exceeded. This intermediary layer filters out correctable errors while preserving detection of permanent defects.
2Productivity
If conventional test apparatus determines memory defective on any detected fail, then productivity is improved by quick rejection, but manufacturing precision deteriorates due to rejection of acceptable memory with correctable errors
Solution Approach 1:
The patent implements dynamic threshold-based evaluation where the failure determination criteria adapt based on the number of detected errors. Instead of a static single-error threshold, the system dynamically evaluates whether the total count of mismatched data sets exceeds a predetermined threshold that accounts for acceptable correctable errors. This dynamic approach maintains quick rejection of clearly defective memory while preserving acceptable memory with correctable errors.
Solution Approach 2:
The patent changes the evaluation parameter from binary (pass/fail on first error) to quantitative (error count versus threshold). By introducing a predetermined threshold value for the number of allowable mismatches, the system transforms the failure criterion into a parameter-based decision that distinguishes between acceptable error rates and definitive defects, thereby improving manufacturing precision without sacrificing test speed.
3Reliability
If test apparatus uses error correction codes in data strings, then reliability is improved by enabling error correction, but device complexity increases due to additional data processing
Solution Approach 1:
The patent applies preliminary action by incorporating error correction codes into the data strings before the testing process begins. The anticipated value includes pre-calculated error correction codes that correspond to the expected data. This preliminary preparation enables the test apparatus to efficiently verify both data integrity and error correction functionality without adding complex real-time processing during the test execution phase.
Data Source
AI summary
A test apparatus is provided for testing memory under test which stores a data string including an error correction code in the form of additional data. The test apparatus comprises: a logic comparator which compares each of the data sets included in a data string read out from the memory under test with a corresponding anticipated value created beforehand; a data error count unit which counts the number of data sets that do not match the respective anticipated values; and a defect detection unit which provides a function whereby, in a case that the count value counted by the error count unit exceeds a predetermined upper limit number which is equal to or greater than 1, determination is made that the memory under test is defective.