Flash Memory Die Pause Circuit for Multi-Die Latency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In memory systems with a single channel or bus between multiple memory dies and a controller, write operations are often interrupted by read commands, leading to re-sending of data and increased latency due to the need to prioritize read commands with strict response times, such as 50 microseconds.
Innovation Solution
The memory system includes a memory die with circuitry that receives a pause command from the controller, allowing it to pause data transfers and maintain register states, enabling the controller to resume data transfers from the point of interruption, thus avoiding complex scheduling mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the controller prioritizes read commands over write commands to meet read response latency requirements, then read response time is improved, but write operation efficiency deteriorates due to interruptions and re-sending of data
Solution Approach 1:
The controller issues a pause command to the first memory die before switching to service the read command on the second memory die. This preliminary action preserves the write operation state without requiring re-sending of data, allowing the controller to service read commands promptly while maintaining write operation continuity.
Solution Approach 2:
The system dynamically switches between memory dies based on command priority. The controller can pause a write operation on one die, service a read command on another die, and then resume the write operation. This dynamic scheduling optimizes read response time while maintaining write efficiency through state preservation.
2Adaptability or versatility
If the controller uses complex scheduling mechanisms to manage multiple memory dies, then command scheduling capability is improved, but system complexity increases
Solution Approach 1:
The memory die itself maintains the state of its registers during paused operations. This self-service approach eliminates the need for the controller to implement complex state tracking and management logic, simplifying the scheduling mechanism while maintaining versatile command scheduling capability.
Solution Approach 2:
The state management function is extracted from the controller and placed in the memory die. By issuing simple pause and resume commands, the controller offloads the burden of state tracking to the memory die, which naturally preserves its register states, thereby reducing controller complexity.
3Reliability
If the controller waits for write operations to complete before servicing read commands, then write operation integrity is improved, but overall system performance deteriorates
Solution Approach 1:
The controller issues a pause command to preserve the write operation state before switching to service read commands. This preliminary action ensures write operation integrity is maintained while allowing read commands to be serviced without waiting, thereby improving overall system performance.
Solution Approach 2:
The write operation continues in the background while the controller services read commands on other memory dies. The paused write operation maintains its state and can be resumed without interruption to its integrity, allowing useful actions (read and write operations) to proceed concurrently, improving overall system performance.
Data Source
AI summary
A memory system and method for simplifying scheduling on a flash interface module and reducing latencies in a multi-die environment are provided. In one embodiment, a memory die is provided comprising a memory array, an interface, at least one register, and circuitry. The circuitry is configured to receive, via the interface, a pause command from a controller in communication with the memory die; and in response to receiving the pause command: pause a data transfer between the memory die and the controller; and while the data transfer is paused and until a resume command is received, maintain state(s) of the at least one register irrespective of inputs received via the interface that would otherwise change the state(s) of the at least one register. Other embodiments are provided.