Flash Memory Cells with Dielectric Protection for Logic Compatibility
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Solution Overview
Problem
The existing methods for forming flash memory cells are not compatible with the formation of logic Metal-Oxide-Semiconductor (MOS) devices, leading to potential damage of the active region during the etching process due to floating gate residue overlapping the logic device region.
Innovation Solution
A dielectric protection layer is formed over the pad oxide layer in the logic device region, which protects the underlying active region and facilitates the removal of floating gate residue, ensuring compatibility with the formation of flash memory cells and preventing damage to the logic MOS device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If existing methods for forming flash memory cells are used, then flash memory cells can be formed, but the active region of logic MOS devices is damaged during the etching process due to floating gate residue overlapping the logic device region
Solution Approach 1:
A dielectric protection layer is introduced as an intermediary between the floating gate residue and the active region of logic MOS devices. This protection layer prevents direct contact and damage during the etching process, allowing the etching to proceed with sufficient precision to remove floating gate residue while protecting the underlying active region from harm.
2Reliability
If a dielectric protection layer is formed over the pad oxide layer in the logic device region, then the active region is protected from damage, but the process complexity increases
Solution Approach 1:
The dielectric protection layer formation is merged with the existing pad oxide layer formation process. By combining these steps and utilizing the same deposition equipment and materials, the additional protection mechanism is integrated into the existing manufacturing flow without requiring separate dedicated process equipment or significantly increasing overall process complexity.
Data Source
AI summary
A method includes forming a first pad oxide layer and a second pad oxide layer over a first active region and a second active region, respectively, of a semiconductor substrate, forming a dielectric protection layer overlapping the first pad oxide layer, removing the second pad oxide layer, and forming a floating gate dielectric over the second active region. A floating gate layer is then formed to include a first portion over the dielectric protection layer, and a second portion over the floating gate dielectric. A planarization is performed on the first portion and the second portion of the floating gate layer. A blocking layer, a control gate layer, and a hard mask layer are formed over the second portion of the floating gate layer. The hard mask layer, the control gate layer, and the blocking layer are patterned to form a gate stack for a flash memory cell.