Multi-Layer Control Dielectric for Flash Memory Scaling
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Solution Overview
Problem
Current flash memory devices face challenges in achieving improved charge blocking characteristics and multi-state memory capabilities with large program/erase voltage windows, leading to limitations in scaling below 40 nm and reliable multi-bit operation.
Innovation Solution
The implementation of a gate stack structure in memory devices, including a charge storage layer between a tunneling dielectric layer and a control dielectric layer, with a charge blocking layer adjacent to the control dielectric layer, featuring a thickness ratio and composition gradient to enhance charge retention and blocking efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If a single layer of Al2O3 is used as the control dielectric layer with thickness less than 20 nm, then the device can be scaled down, but charge transport is not completely blocked leading to program and erase saturation at lower voltage windows
Solution Approach 1:
The control dielectric layer is divided into multiple sub-layers (first control dielectric sub-layer, second control dielectric sub-layer, and third control dielectric sub-layer) with different dielectric constants. This segmentation allows each sub-layer to contribute differently to charge blocking, with lower-k sub-layers providing better blocking and higher-k sub-layers enabling thinner overall structure for scaling.
Solution Approach 2:
The control dielectric layer uses a composite structure combining materials with different dielectric constants (k values). The first sub-layer has k between 3-6, the second has k between 6-10, and the third has k between 10-25. This composite approach optimizes both charge blocking (using lower-k materials) and device scaling (using higher-k materials strategically).
2Length of moving object
If the control dielectric layer thickness is reduced to enable down-scaling below 40 nm, then device scaling is achieved, but charge blocking efficiency decreases leading to saturation
Solution Approach 1:
Different regions of the control dielectric layer have different dielectric properties tailored to local needs. The sub-layers adjacent to the charge storage layer use lower-k materials for superior charge blocking, while sub-layers closer to the control gate can use higher-k materials. This local optimization ensures charge blocking where needed while maintaining overall thinness for scaling.
3Adaptability or versatility
If conventional control dielectric layers are used, then device structure is simple, but multi-state memory capabilities with large program/erase voltage windows cannot be achieved
Solution Approach 1:
The control dielectric layer is segmented into multiple sub-layers with progressively increasing dielectric constants from the charge storage layer interface toward the control gate. This segmentation creates distinct functional zones that enable multi-state operation with large voltage windows while maintaining a relatively compact overall structure.
Solution Approach 2:
The dielectric constant parameter is systematically varied across the control dielectric layer thickness. By changing the k value from 3-6 in the first sub-layer to 6-10 in the second, and 10-25 in the third, the structure achieves enhanced charge blocking and expanded voltage windows necessary for multi-state memory without excessive complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in improved charge retention of 85% or greater over 24 hours at 250°C, expanded program/erase windows, and increased reliability for multi-bit storage, enabling efficient operation in smaller node sizes and multi-state memory applications.
Implementation Method 1
High-k dielectric layers can serve as efficient charge-blocking layers. They have been used as the control dielectric layer for flash memory devices
Implementation Method 2
A flash memory device stores information in a charge storage layer that is separated from a 'control gate.' A voltage is applied to the control gate to program and erase the memory device by causing electrons to be stored in, and discharged from, the charge storage layer.
Data Source
AI summary
Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide, hafnium oxide, and/or hybrid films of hafnium aluminum oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multi state (e.g., two, three or four bit) operation.