Flash Memory Program Disturb Reduction via Differential Verify Levels
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Solution Overview
Problem
Existing flash memory systems face challenges in reducing program disturb, where unselected memory cells adjacent to the selected word line can be inadvertently programmed, leading to errors due to Gate Induced Drain Leakage (GIDL) and voltage coupling issues, despite existing techniques like self-boosting and Erased Area Self Boosting not fully eliminating the problem.
Innovation Solution
Implementing a system that uses different verify levels and read compare values for specific word lines or groups of storage elements based on their position relative to a boosted region, allowing for targeted programming and reading to minimize threshold voltage shifts and reduce program disturb effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If self-boosting or Erased Area Self Boosting techniques are used during programming, then the voltage coupling issues are partially mitigated, but program disturb errors still occur due to Gate Induced Drain Leakage and threshold voltage shifts in unselected memory cells
Solution Approach 1:
The patent applies different verify levels to different word lines based on their position relative to the selected word line. Specifically, word lines adjacent to the selected word line use a first verify level, while other word lines use a second verify level. This localized differentiation addresses the varying susceptibility of different memory cells to program disturb, with adjacent word lines receiving more stringent verification to compensate for their higher vulnerability to GIDL effects.
Solution Approach 2:
The patent changes the verify level parameter during programming operations. By implementing a first verify level for word lines adjacent to the selected word line and a second verify level for other word lines, the system dynamically adjusts the verification threshold based on the specific word line being programmed. This parameter change allows the system to maintain data integrity while reducing false program disturb errors.
2Manufacturing precision
If higher verify levels are used for all word lines during programming, then programming accuracy improves, but the impact of program disturb on adjacent word lines increases due to voltage coupling
Solution Approach 1:
The patent implements differential verify levels where word lines adjacent to the selected word line use a first verify level that is less than a second verify level used by other word lines. This localized quality approach ensures that word lines most susceptible to voltage coupling effects receive less stringent verification, thereby reducing false program disturb errors while maintaining adequate programming accuracy for other word lines.
Solution Approach 2:
The patent segments the memory array into different groups based on their proximity to the selected word line. Word lines adjacent to the selected word line are segmented into a first group with a first verify level, while other word lines form a second group with a second verify level. This segmentation allows the system to tailor verification strategies to the specific electrical characteristics of each group, optimizing both programming accuracy and disturbance reduction.
3Object-affected harmful factors
If different verify levels are implemented for different word lines, then program disturb impact is reduced, but system complexity increases due to additional control logic
Solution Approach 1:
The patent applies a simple positional rule to determine verify levels: word lines adjacent to the selected word line use a first verify level, while all other word lines use a second verify level. This local quality approach based on geometric position provides a straightforward implementation method that minimizes control logic complexity while effectively reducing program disturb impact through differentiated verification.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the impact of program disturb by shifting threshold voltage distributions to align with those of other memory cells, minimizing errors and maintaining data integrity during programming and reading operations.
Implementation Method 1
unselected memory cells adjacent to the selected word line can be inadvertently programmed, leading to errors due to Gate Induced Drain Leakage (GIDL) and voltage coupling issues
Data Source
AI summary
The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as “program disturb.” A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different verify levels are used for a particular word line (or other grouping of storage elements) during a programming process. In another embodiment, different compare levels are used for a particular word (or other grouping of storage elements) during a read process.