Flash Memory Double Output Pipelined Read Speed

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Solution Overview

Problem

Flash memory devices have slower read times compared to volatile memory technologies, necessitating an improvement in effective read speed for non-volatile memory devices.

Innovation Solution

Implementing a non-volatile memory device with a core array of memory cells and utilizing double output memories to perform random multi-page read operations in a pipelined manner, where data is processed simultaneously through volatile memory to enhance read speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If Flash memory is used for non-volatile storage, then data retention without power is achieved, but read speed is slower compared to volatile memory

Engineering Contradiction:

Improvedata retentionVSAvoidread speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The output memory is divided into two separate memory structures (first output memory and second output memory) that operate in parallel pipeline stages. This segmentation allows simultaneous data transfer operations to occur, effectively doubling the read throughput while maintaining the non-volatile Flash memory's data retention capabilities.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Data is pre-loaded into the first output memory from the core array while simultaneously being transferred to the second output memory. This preliminary action in the first pipeline stage enables the second pipeline stage to immediately output data without waiting for the core array read operation to complete, achieving overlapping execution and improved read speed.

Inventive Principle:

Principle #10Preliminary action

2Productivity

If conventional single memory output is used, then device complexity is lower, but effective read speed is limited

Engineering Contradiction:

Improveeffective read speedVSAvoidmemory structure complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The dual-output-memory architecture enables continuous data output by maintaining active pipeline stages. While the first pipeline stage transfers data from the core array to the first output memory, the second pipeline stage simultaneously outputs data from the second output memory, ensuring uninterrupted data flow and maximizing effective read speed.

Inventive Principle:

Principle #20Continuity of useful action

Solution Approach 2:

The patent introduces a temporal dimension to the data output process by implementing pipelined operation across two memory structures. Instead of sequential single-memory operations, the system operates in parallel time slices with overlapping stages, effectively adding a time-based dimension to the data retrieval process that doubles throughput.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS7423915B2Random cache read using a double memory

Publication Date: 2008.09.09 MONTEREY RESEARCH LLC

AI summary

A non-volatile memory, such as a Flash memory, is configured to perform a random multi-page read operation. The memory may include a core array of non-volatile memory cells and input lines for receiving an indication of the random multi-page read operation. Further, the memory may include a multi-level volatile memory coupled to the core array that is configured to simultaneously process multiple pages of data from the core array in a pipelined manner. Output lines are coupled to the multi-level volatile memory and output the pages of data from the memory device.