Flash Memory DPD Controller for Staged Standby Power Down

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Solution Overview

Problem

Conventional semiconductor devices require an external command to transition from standby mode to deep power down mode, limiting power consumption reduction and increasing recovery time, especially as element size shrinks and internal power supply voltage detection consumes power.

Innovation Solution

A semiconductor device with a DPD controller that automatically transitions from standby mode to deep power down mode by generating multiple power down enable signals based on elapsed time, blocking power supply to internal circuits in stages, allowing for reduced power consumption without user input.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If the flash memory enters DPD mode by blocking internal voltage supply to reduce power consumption, then power consumption is drastically reduced, but a certain amount of time is required for the cut off circuit to operate normally

Engineering Contradiction:
Improvepower consumptionVSAvoidrecovery time
Core Design Contradiction:
Loss of energyVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-charging the internal voltage node before blocking the voltage supply when entering DPD mode. This ensures that the internal circuit maintains sufficient voltage for a predetermined period, allowing the device to respond to commands during this window. The voltage supply is blocked in advance of complete power depletion, creating a buffer period that reduces recovery time while maintaining power savings.

Inventive Principle:
Principle #10Preliminary action

2Ease of operation

If the internal power supply voltage is used in standby mode, then the command can be immediately responded to, but the internal power supply voltage detection circuit must be operated consuming a certain degree of power

Engineering Contradiction:
Improvecommand response capabilityVSAvoidpower consumption
Core Design Contradiction:
Ease of operationVSLoss of energy

Solution Approach 1:

The patent applies partial action by providing power to only specific circuits needed for command detection and processing during standby mode, rather than powering all internal circuits. The voltage supply control unit selectively powers the command detection circuit while leaving other circuits in a low-power state, reducing overall power consumption while maintaining the ability to respond to commands.

Inventive Principle:
Principle #16Partial or excessive action

3Loss of energy

If the flash memory supports the DPD command for transitioning to deep power down mode, then power consumption can be reduced, but devices that do not support the DPD command cannot achieve the same power savings

Engineering Contradiction:
Improvepower consumptionVSAvoidcompatibility
Core Design Contradiction:
Loss of energyVSAdaptability or versatility

Solution Approach 1:

The patent applies universality by implementing a voltage supply control unit that can operate in multiple modes: it can respond to DPD commands when available, automatically transition to DPD mode when no command is received, or maintain standby mode operation. This multi-functional approach ensures compatibility with both DPD-capable and non-DPD devices while enabling power consumption reduction across all device types.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11496118B2Semiconductor device
Publication Date: 2022.11.08 WINBOND ELECTRONICS CORP
  • US11496118B2 patent drawing
  • US11496118B2 patent drawing
  • US11496118B2 patent drawing

AI summary

A semiconductor device that can automatically transition from a standby mode to a deep power down (DPD) mode is provided. The semiconductor device includes a DPD controller supporting the DPD mode and multiple internal circuits. The DPD controller measures a time since a time point of entering the standby mode and generates multiple power down enable signals for further reducing power consumption in the standby mode in response to elapse of a measurement time, so that operations of the multiple internal circuits are stopped in stages.