Flash Memory DPD Recovery via Segmented Power Paths
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Solution Overview
Problem
Conventional flash memory systems require a dedicated command to exit the deep power-down (DPD) mode, leading to longer recovery times due to high load capacitance in internal circuits, which increases power consumption and reduces efficiency.
Innovation Solution
Implementing a method where the DPD mode is automatically released by inputting a standard command such as reading, programming, or erasing, allowing power to be supplied to specific circuit portions through separate current paths, enabling them sequentially to reduce recovery time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dedicated DPD release command is used to exit deep power-down mode, then the DPD mode can be reliably released, but the recovery time is prolonged due to high load capacitance in internal circuits
Solution Approach 1:
The internal circuit is divided into multiple circuit portions, each with its own separate current path. When exiting DPD mode, power can be supplied to different circuit portions independently and sequentially, rather than all at once, which reduces the total load capacitance that needs to be charged simultaneously and thereby reduces recovery time.
Solution Approach 2:
The standard command input circuit is designed to automatically trigger the DPD release sequence when a standard command is detected. This preliminary action prepares the system for quick recovery by having the command recognition circuit ready to initiate the power supply sequence to different circuit portions without waiting for a dedicated release command.
2Productivity
If power is supplied to all internal circuits simultaneously upon DPD release, then all circuits can operate at full capacity, but the recovery time increases due to high total load capacitance
Solution Approach 1:
The internal circuit is segmented into multiple portions with separate current paths. Power is supplied to these portions sequentially rather than simultaneously, which reduces the peak current demand and total effective load capacitance at any given moment, thereby reducing recovery time while still ensuring all circuits eventually reach full operational capacity.
Solution Approach 2:
The power supply system dynamically adjusts which circuit portions receive power and when, based on the operational requirements. This dynamic power management allows the system to optimize the recovery process by supplying power to critical circuit portions first, then to less critical portions, achieving full productivity with minimized recovery time.
3Productivity
If the internal circuit is enabled quickly after DPD mode release, then productivity is improved, but power consumption increases due to incomplete shutdown of off-leakage current paths
Solution Approach 1:
By segmenting the internal circuit into multiple portions with separate current paths, the system can selectively enable only the necessary circuit portions for the current operation. This segmentation allows for faster recovery of critical functions while keeping other portions in a low-power state, thereby reducing overall off-leakage current consumption.
Solution Approach 2:
The system applies partial action by enabling only the minimum necessary circuit portions required for the current operation rather than enabling the entire internal circuit. This partial enablement achieves sufficient productivity for the task at hand while minimizing power consumption from off-leakage currents in non-essential circuits.
Data Source
AI summary
A semiconductor storing apparatus and a flash memory operation method, for shortening a recovery time from a deep power-down (DPD) mode without a dedicated command for the DPD are provided. A flash memory includes: a standard command interface circuit and a DPD controller, operating through an external power voltage; a voltage supply node, for supplying power from the external power voltage via a first current path; a voltage supply node, for supplying power from the external power voltage via a second current path; an internal circuit group, connected to the voltage supply node; and a charge pump circuit, connected to the voltage supply node. When the DPD mode is released, the internal circuit group is enabled after the charge pump circuit is enabled.