Flash Memory Integrity Verification Using Dual MAC Algorithms

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Solution Overview

Problem

Existing memory integrity verification methods in controllers (MCU, ECU) face challenges in securing the integrity of all data, especially against hash function attacks, and cannot detect manipulation of non-targeted data effectively.

Innovation Solution

A system and method utilizing at least two types of MAC algorithms in parallel to verify memory integrity, where a secure memory module stores multiple key values, and an integrity verifier generates and compares MAC values using a data table to detect data manipulation, replacing manipulated data with a default value if mismatched.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If only selected main data is targeted for MAC value generation and verification, then verification efficiency is improved, but integrity of non-selected data cannot be secured

Engineering Contradiction:
Improveverification efficiencyVSAvoidintegrity coverage
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments data verification into two distinct layers: (1) MAC-based verification for selected main data groups to ensure efficiency, and (2) hash function-based verification for all data including non-selected data to ensure comprehensive integrity coverage. This segmentation allows each verification method to operate on its appropriate scope without compromising overall security or efficiency

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies partial action by using MAC verification only on critical main data groups where high-speed verification is most beneficial, while applying hash function verification to all data to provide comprehensive coverage. This selective application of different verification strengths optimizes both efficiency and reliability

Inventive Principle:
Principle #16Partial or excessive action

2Speed

If a single MAC algorithm is used for verification, then processing speed is improved, but vulnerability to hash function attacks increases

Engineering Contradiction:
Improveprocessing speedVSAvoidattack resistance
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent employs a composite verification approach by combining two different cryptographic algorithms (MAC and hash functions) with distinct security characteristics. The MAC algorithm provides fast verification for critical data, while the hash function provides strong attack resistance for comprehensive data protection, creating a composite security system that leverages the strengths of both approaches

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The patent changes the verification parameter (algorithm type) based on the data category and security requirements. For main data groups, it uses MAC algorithms with faster processing speed, while for all data including non-main data, it uses hash functions with stronger attack resistance properties, thus adapting the verification parameter to match the specific security needs of each data subset

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12547319B2System and method for verifying memory integrity
Publication Date: 2026.02.10 HYUNDAI MOBIS CO LTD
  • US12547319B2 patent drawing
  • US12547319B2 patent drawing
  • US12547319B2 patent drawing

AI summary

Methods and apparatuses for ensuring integrity of stored data in a flash memory, where a system for verifying memory integrity includes a secure memory module configured to store two or more key values for generating a message authentication code (MAC) value, an integrity verifier configured to generate a MAC value through two or more pre-stored MAC processes using a data table based on an analysis of data stored in a corresponding memory area and any one key value selected from the secure memory module according to a criterion and to compare the generated MAC value and a stored MAC value that is matched with a corresponding key value, and a verification processor configured to determine that data manipulation has occurred, in response to the generated MAC value and the stored MAC value not matching using a result of the comparison, and to perform a preset operation.