Flash Memory Error Correction via Dual-Read Voltage Comparison
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Solution Overview
Problem
High integration density in flash memory devices leads to increased interference between cells, reduced read margins, and shortened device life due to deteriorating oxide layers, affecting data retention and reliability.
Innovation Solution
A dual-read operation error correction method is implemented, where a first and second non-selection read voltage are applied to unselected memory cells to detect and correct errors by comparing data sensed in both operations, thereby inverting error bits and improving data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If integration density is increased to store more data, then storage capacity is improved, but interference between cells increases and read margin is reduced
Solution Approach 1:
The patent applies preliminary action by performing a first read operation before the second read operation to obtain reference data. This preliminary read establishes a baseline that is used to correct errors in the subsequent read, thereby maintaining read reliability despite reduced read margins caused by high integration density
Solution Approach 2:
The patent implements feedback by comparing data from the first read operation with data from the second read operation. The comparison result is used to identify and correct error locations, creating a feedback loop that compensates for the reduced read margin and interference effects in highly integrated memory cells
2Quantity of substance
If integration density is increased to store more data, then storage capacity is improved, but device life is shortened due to oxide layer deterioration
Solution Approach 1:
The patent performs a preliminary read operation that applies a first non-selection read voltage to unselected memory cells. This preliminary action characterizes the data retention characteristics of the oxide layer before actual data reading, allowing for error correction that compensates for oxide layer deterioration and extends effective device life
Solution Approach 2:
The patent uses feedback from comparing first and second read data to detect error locations caused by oxide layer deterioration. This feedback mechanism enables continuous error correction throughout the device's operational life, effectively extending the usable duration of the memory device despite ongoing oxide layer degradation
3Reliability
If dual-read operation is performed to correct errors, then data reliability is improved, but reading time is increased
Solution Approach 1:
The patent performs the first read operation as a preliminary step that characterizes data retention characteristics. Although this adds time, it enables error detection and correction in the subsequent read, ultimately improving data reliability without requiring multiple full reads
Solution Approach 2:
The patent implements efficient feedback by comparing read data to identify error locations and inverting only the erroneous bits. This targeted correction approach minimizes the additional time required compared to exhaustive error checking methods, balancing data reliability improvement with acceptable reading time overhead
Data Source
AI summary
A method for correcting read data error of a nonvolatile memory device, the error correction method including performing a first read operation of applying a first non-selection read voltage to a plurality of unselected memory cells to read a plurality of selected memory cells, performing a second read operation of applying a second non-selection read voltage less than the first non-selection read voltage to the unselected memory cells to read the selected memory cells, and comparing data sensed in the first and second read operations to detect error locations of read data.