Flash Memory Program Verification Using Dual Verify Voltages
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Solution Overview
Problem
Conventional programming methods for multi-level cell (MLC) flash memory devices struggle to reduce the width of threshold voltage distribution without increasing programming time, which limits the storage capacity and efficiency of these devices.
Innovation Solution
A program verifying method that employs two verify voltages, a first verify voltage and a second verify voltage with a lower magnitude, to reduce the step voltage magnitude and programming time, by controlling the sensing current and evaluation time, allowing for a double verify operation to effectively narrow the threshold voltage distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the magnitude of step voltage is reduced to narrow threshold voltage distribution, then the width of threshold voltage distribution is reduced, but programming time increases due to more program pulses
Solution Approach 1:
The verification process is segmented into two distinct operations: a first verify operation using a higher verify voltage to quickly identify cells needing programming, and a second verify operation using a lower verify voltage to precisely narrow the threshold voltage distribution. This segmentation allows each verification stage to use optimized voltage levels for its specific purpose, resolving the contradiction between distribution width and programming time.
Solution Approach 2:
The first verify operation using the higher verify voltage performs a preliminary identification of memory cells that require programming. By pre-identifying these cells before applying program pulses, the system can efficiently target only the necessary cells with the reduced step voltage in subsequent operations, avoiding unnecessary programming cycles and reducing overall programming time while still achieving narrow threshold voltage distribution.
2Manufacturing precision
If conventional single verify voltage method is used, then verification is simpler, but threshold voltage distribution width cannot be effectively reduced
Solution Approach 1:
The verification process is divided into two distinct operations with different voltage levels and purposes. The first verify operation uses a higher voltage for initial cell identification, while the second verify operation uses a lower voltage for precise threshold voltage control. This segmentation enables effective threshold voltage distribution narrowing while maintaining manageable complexity through clear separation of verification stages.
Solution Approach 2:
The verification method changes the verify voltage parameter between two different operations. By using a higher verify voltage in the first operation and a lower verify voltage in the second operation, the system can achieve both effective threshold voltage distribution narrowing and efficient programming. This parameter change strategy resolves the contradiction by optimizing voltage selection for each specific verification stage.
Data Source
AI summary
A duel program verify operation is performed using first and second verify voltages. In order to reduce the width of a threshold voltage distribution during an incremental step pulse program implementation, data of a corresponding memory cell are verified twice using the first verify voltage and the second verify voltage. During a second verify operation using the second verify voltage, a sensing current is adjusted by controlling voltages applied as a bit line select signal and an evaluation time period. Therefore, the threshold voltage of the memory cell can be measured higher or lower than its actual value and the width of a threshold voltage distribution is reduced.