Flash Memory Dummy Cell for Leakage Control
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Solution Overview
Problem
In NAND-type flash memory, the miniaturization of components leads to gate-induced drain leakage (GIDL), causing writing errors and threshold voltage changes, and increasing memory capacity through more blocks results in slower operation speeds due to increased load capacitance, particularly in multi-plane configurations where shared driving control circuits can inadvertently affect unselected planes, leading to unexpected current flow and memory cell threshold voltage distribution issues.
Innovation Solution
A method and structure where a dummy cell is programmed in the NAND string of an unselected plane to prevent unexpected current flow by turning off the select transistors in the unselected plane, ensuring the dummy cell is arranged between the select transistor and the memory cell, and controlled by a controller to apply programming voltages to the dummy word line, thereby maintaining the stability of memory cell threshold voltage distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of blocks is increased to increase memory capacity, then the memory capacity increases, but the operation speed decreases due to increased load capacitance of the global bit line
Solution Approach 1:
The memory cell array is divided into multiple planes, with each plane containing a subset of blocks. This segmentation allows the global bit line to serve smaller groups of blocks simultaneously, reducing the load capacitance per operation while maintaining high total memory capacity across all planes.
2Quantity of substance
If miniaturization is implemented to increase memory density, then memory capacity increases, but gate-induced drain leakage occurs causing writing errors and threshold voltage changes
Solution Approach 1:
A dummy cell is introduced as an intermediary component between the select transistor and the actual memory cell. This dummy cell acts as a buffer that prevents direct interaction between the select transistor and memory cell, thereby eliminating the GIDL effect while allowing the memory cell to function correctly.
3Device complexity
If a shared driving control circuit is used to control multiple planes, then device complexity is reduced, but unexpected current flow occurs in unselected planes affecting threshold voltage distribution
Solution Approach 1:
The dummy cell serves as an intermediary that blocks unexpected current flow in unselected planes. When the shared driving control circuit applies control signals to multiple planes, the dummy cell in unselected planes prevents current from flowing through the select transistor, thereby maintaining stable threshold voltage distribution without requiring separate control circuits for each plane.
Data Source
AI summary
A flash memory having high reliability and a method for controlling the flash memory is provided for seeking stability of memory cell threshold voltage distribution. A NAND string of the flash memory has: a source-line-side select transistor; a source-line-side dummy cell; a plurality of memory cells; a bit-line-side dummy cell; and a bit-line-side select transistor. A method for controlling the flash memory includes the following step: after erasing a selected block, programming the dummy cell of the selected block into a programmed state by applying a programming voltage to a dummy word line which is connected to the dummy cell.