Flash Memory Dummy Cells Reduce Coupling Capacitance
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Solution Overview
Problem
Flash memory devices with conventional All Bit Line (ABL) architecture require increased program verification and read times due to coupling capacitances between adjacent bit lines, leading to potential incorrect read operations when programmed or erased cells share the same word line.
Innovation Solution
The implementation of multiple strings in a flash memory device, where each string includes first memory cells and second memory cells, with one second memory cell set to a programmed state and the remaining set to an erased state, known as dummy cells, which are used to reduce coupling capacitances by pre-charging all bit lines simultaneously, thereby eliminating the need for repeated verify and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional ABL architecture is used to program memory cells of a selected word line and all bit lines at one time, then programming capability is improved, but coupling capacitances between adjacent bit lines cause incorrect read operations and require repeated verify and read operations, increasing operation time
Solution Approach 1:
The patent applies preliminary action by pre-charging bit lines before read operations and using dummy cells in advance to compensate for coupling capacitance effects. The dummy cells are programmed or erased beforehand to create appropriate voltage levels that counteract the coupling capacitance interference during subsequent read operations, eliminating the need for repeated verify cycles.
Solution Approach 2:
The patent introduces dummy cells as intermediary elements between the actual memory cells and the bit lines. These dummy cells act as mediators that absorb or compensate for the coupling capacitance effects, allowing accurate read operations without requiring repeated verification. The dummy cells serve as a buffer that isolates the interference from affecting the actual data readout.
2Reliability
If repeated verify and read operations are performed to account for coupling capacitances, then read accuracy is improved, but operation time increases
Solution Approach 1:
The patent performs preliminary compensation for coupling capacitance effects by programming or erasing dummy cells before read operations. This preliminary action establishes the correct voltage baseline on bit lines, ensuring that subsequent read operations are accurate without requiring repeated verify cycles to detect and correct errors.
Solution Approach 2:
The patent converts the harmful coupling capacitance effect into a beneficial mechanism by using dummy cells to generate compensating voltage signals. The coupling capacitance that causes interference is transformed into a useful effect where the dummy cells' charge/discharge states actively counterbalance the interference, enabling single-pass accurate reads.
3Object-affected harmful factors
If dummy cells are programmed or erased to compensate for coupling capacitances, then coupling capacitance effects are reduced, but device complexity increases
Solution Approach 1:
The patent segments the memory structure by dividing it into actual memory cells and separate dummy cells. This segmentation allows the dummy cells to be independently programmed or erased to compensate for coupling capacitance effects on specific bit lines, reducing interference without requiring complex control mechanisms for the entire memory array.
Solution Approach 2:
The dummy cells serve multiple functions: they compensate for coupling capacitance effects, provide voltage compensation during read operations, and can be integrated into the existing memory block structure without requiring entirely new architecture. This multi-functionality reduces the need for additional complex compensation circuits or mechanisms.
Data Source
AI summary
Disclosed is a flash memory device having multiple strings, where each string includes first memory cells and second memory cells. One second memory cell of the second memory cells in each string is set to a programmed state, and remaining second memory cells are set to an erased state.