Flash Memory Dummy Transistors With Selective Thresholds
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Solution Overview
Problem
The integration density of flash memory devices is limited by the need for separate bit lines for each memory cell string, which restricts the capacity and efficiency of semiconductor memory devices, and there is a growing demand for higher capacity and reliability in flash memory devices.
Innovation Solution
The implementation of a common bit line structure using serially-connected memory cells and dummy transistors with different threshold voltages, coupled through a control circuit that selectively programs and erases the dummy transistors to enhance integration density and reduce fabrication costs, while maintaining data retention without power supplies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate bit lines are used for each memory cell string, then reliability is improved, but integration density deteriorates
Solution Approach 1:
Multiple memory cell strings share a common bit line, merging previously separate resources. This reduces the total number of bit lines needed, increasing integration density while maintaining reliable data transmission through the shared resource
Solution Approach 2:
The common bit line serves multiple memory cell strings simultaneously, making it a universal resource. This multi-functional approach allows a single bit line to handle data transmission for several strings, improving density without sacrificing reliability
2Area of moving object
If dummy transistors with different threshold voltages are used, then integration density is improved, but device complexity increases
Solution Approach 1:
Dummy transistors are assigned different threshold voltages based on their specific position and function within the memory cell string. This localized differentiation optimizes performance for each transistor's role while maintaining overall system efficiency
Solution Approach 2:
The threshold voltage parameter of dummy transistors is varied to achieve desired electrical characteristics. By adjusting this key parameter, the patent optimizes device performance and integration density without fundamentally changing the device architecture
3Area of moving object
If multiple memory cell strings share a common bit line, then integration density is improved, but control complexity increases
Solution Approach 1:
Dummy transistors act as intermediary elements between the common bit line and individual memory cell strings. These intermediaries enable selective control and isolation of strings, managing control complexity while maintaining the benefits of shared bit lines
Solution Approach 2:
The common bit line system is segmented into multiple independently controllable sections through dummy transistors. This segmentation allows selective activation of specific memory cell strings, reducing control complexity by enabling targeted operations rather than global control
Data Source
AI summary
Flash memory devices include a first memory cell string including a plurality of serially-connected memory cells and first and second serially-connected dummy transistors configured to couple the serially-connected memory cells to a bit line and a second memory cell string including a plurality of serially-connected memory cells and first and second serially-connected dummy transistors configured to couple the serially-connected memory cells to the bit line. The first dummy memory cells of the first and second memory cell strings have gates connected in common to a first dummy word line and have different threshold voltages and the second dummy memory cells of the first and second memory cell strings have gates connected in common to a second dummy bit line and have different threshold voltages. In some embodiments, the first dummy memory cell of the first memory cell string and the second dummy memory cell of the second memory cell string may have threshold voltages greater than a predetermined voltage and the second dummy memory cell of the first memory cell string and the first dummy memory cell of the second memory cell string may have threshold voltages less than the predetermined voltage.