Flash Memory Write Latency via Dynamic Addressing
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Solution Overview
Problem
Conventional flash memory writing operations require multiple steps, including erasure and programming, which increase write latency due to the need to change the logic state of cells, resulting in inefficient data storage and retrieval times.
Innovation Solution
Dynamic addressing schemes that map logical addresses to physical addresses, ensuring each write operation occurs in a previously erased location, reducing the need for separate erasure and write operations by grouping physical addresses into blank, valid, and used pools, and utilizing a global sequence number for recovery after power failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional flash memory writing operations are used (erase then program), then data can be stored in flash memory cells, but write latency increases due to multiple operations required
Solution Approach 1:
The system performs preliminary actions by pre-erasing memory blocks in advance and maintaining a pool of ready-to-write blocks. When a write operation is needed, pre-erased blocks are immediately available, eliminating the erase wait time from the critical write path.
Solution Approach 2:
The memory system is segmented into multiple pools (pre-erased pool, valid data pool, obsolete data pool) with dedicated functions. This segmentation allows write operations to target only the pre-erased pool, separating the erase operation from the write operation and enabling them to occur at different times.
2Productivity
If dynamic addressing with address mapping is implemented, then write operations can occur in previously erased locations, but device complexity increases due to mapping tables and management overhead
Solution Approach 1:
Different regions of the address space are assigned different qualities/functions: the pre-erased pool accepts new writes, the valid data pool stores current data, and the obsolete data pool holds erased blocks. This local differentiation simplifies management by giving each region a specific purpose.
Solution Approach 2:
The address mapping table acts as an intermediary between logical addresses and physical memory locations. It translates high-level write requests into physical addresses in the pre-erased pool, abstracting the complexity of memory management from the write operation.
3Loss of time
If logical addresses are mapped to physical addresses dynamically, then each write can occur in a single operation, but the system requires additional structures to track and manage address mappings
Solution Approach 1:
The system implements self-service through automatic block selection from the pre-erased pool and automatic updating of the address mapping table. The controller autonomously manages the complexity of tracking which blocks are erased and ready for writing, without requiring external intervention.
Solution Approach 2:
The address mapping is dynamic rather than static, allowing the system to adaptively allocate physical blocks from the pre-erased pool as needed. The mapping table is continuously updated to reflect current allocations, enabling flexible and efficient write operations.
Data Source
AI summary
A technique includes performing a plurality of write operations to store data in different physical memory locations. Each of the physical memory locations are associated with a logical address that is shared in common among the physical addresses. The technique includes storing sequence information in the physical memory locations to indicate which one of the write operations occurred last.