Flash Memory Dynamic Addressing for Write Latency and Failure Recovery
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Solution Overview
Problem
Conventional flash memory technologies require multiple operations for writing data, including erasing and programming, which increases write latency due to the need for two separate memory operations, and face challenges in recovering logical-to-physical address mappings after a power failure.
Innovation Solution
Dynamic addressing schemes that group physical addresses into blank, valid, and used pools, allowing for single-write operations by mapping logical addresses to erased locations and using sequence numbers to reconstruct mappings post-failure, along with checkpointing mechanisms to ensure data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional flash memory uses two separate operations (erase and program) to write data, then data can be stored in the memory cell, but write latency increases due to the multiple operations required
Solution Approach 1:
The system performs preliminary actions by pre-erasing memory blocks in advance and maintaining a translation layer that tracks logical-to-physical address mappings. This allows write operations to directly program data into pre-prepared erased blocks without requiring an erase operation at the time of writing, thereby reducing write latency while maintaining data storage reliability
Solution Approach 2:
The patent introduces a translation layer as an intermediary between the host system and the flash memory. This translation layer maintains a translation table that maps logical addresses to physical addresses, enabling the system to write data to pre-erased physical blocks while the host sees continuous logical addresses. The intermediary absorbs the complexity of erase-program sequencing, allowing fast writes without compromising data integrity
2Loss of time
If dynamic addressing is used to map logical addresses to physical addresses in non-volatile memory, then write latency is reduced by enabling single-write operations, but the system faces challenges in recovering address mappings after power failure
Solution Approach 1:
The system creates and maintains a copy of the address mapping information in a translation table stored in non-volatile memory. This translation table serves as a persistent copy of the logical-to-physical address mappings, allowing the system to recover the mapping information after power failure by simply reading the translation table, rather than having to reconstruct mappings from scratch
Solution Approach 2:
The patent implements checkpointing mechanisms that periodically save the state of the translation table to non-volatile memory before potential failures can occur. These checkpoints act as a cushion against data loss, ensuring that even if power fails during operation, the system can recover from the most recent checkpoint and reconstruct the translation table without losing address mapping information
3Reliability
If checkpointing mechanisms are implemented to ensure data integrity after power failure, then recovery capability is improved, but system complexity increases due to additional recovery procedures
Solution Approach 1:
The patent extracts the complexity of recovery procedures into a separate, dedicated recovery module that operates independently from the main data path. The checkpointing and recovery logic is isolated as a distinct subsystem that only activates upon detecting power failure or corruption events. This modular extraction allows the main write operations to remain simple and fast, while robust recovery capabilities are available when needed without adding ongoing complexity to normal operation
Data Source
AI summary
Write operations store data in different physical memory locations. Each of the physical memory locations are associated with a logical address that is shared in common among the physical addresses. Sequence information stored in the physical memory location indicates which one of the write operations occurred last. The available erased memory location can be split into a list of erased memory locations available to be used and a list of erased memory locations not available to be used. Then, on a failure, only the list of erased memory locations available to be used needs to be analyzed to reconstruct the consumption states of memory locations.