Dynamic Read Voltage Adjustment for Flash Memory Error Correction
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Solution Overview
Problem
Existing memory devices face challenges in correcting double-bit or multi-bit errors, which can lead to reduced yield and reliability during manufacturing and operational life, as Error Correction Code (ECC) techniques can detect but not correct such errors, resulting in uncorrectable failures.
Innovation Solution
A dynamic read scheme is implemented where the read voltage level is adjusted in both directions to attempt to read double-bit or multiple-bit errors, allowing for the correction of previously uncorrectable errors by selecting a new read voltage level that either corrects all bits within an ECC section or reduces errors to a single-bit level correctable by ECC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If ECC techniques are used to detect errors, then error detection capability is improved, but the ability to correct double-bit or multi-bit errors deteriorates
Solution Approach 1:
The patent applies dynamics by making the read voltage level adjustable and changeable during operation. The system dynamically selects between a first read voltage level (for normal reads) and a second read voltage level (for salvage operations), allowing the memory device to adapt its reading characteristics to correct previously uncorrectable errors while maintaining normal operation under standard conditions.
Solution Approach 2:
The patent changes the read voltage level parameter to resolve the contradiction. By switching between different voltage levels, the system alters the electrical characteristics of the memory cells during reading, enabling the conversion of uncorrectable multi-bit errors into correctable single-bit errors while preserving the original ECC detection capability.
2Device complexity
If a fixed read voltage level is used, then device simplicity is improved, but the ability to correct extrinsic bits deteriorates
Solution Approach 1:
The system transitions from a static fixed voltage approach to a dynamic selective voltage approach. The read voltage level is determined based on whether a salvage operation is needed, allowing the device to maintain simplicity during normal operation while gaining enhanced correction capability when required.
Solution Approach 2:
The read voltage level parameter is changed from a single fixed value to a selectable set of values. This allows the memory device to optimize its reading characteristics for different operational modes (normal vs. salvage) without permanently increasing the complexity of the underlying memory structure.
3Reliability
If multiple read voltage levels are implemented, then error correction capability is improved, but device complexity increases
Solution Approach 1:
The patent implements a dynamic voltage selection mechanism that chooses between two read voltage levels based on operational mode. This dynamic approach enables enhanced error correction capability through voltage variation while avoiding the complexity of implementing multiple simultaneous voltage generation and switching circuits for all read operations.
Solution Approach 2:
The system uses parameter changes in the read voltage level to achieve improved error correction. By selectively applying different voltage levels rather than permanently configuring the device with complex multi-voltage infrastructure, the patent achieves better reliability with minimal increase in device complexity.
Data Source
AI summary
In accordance with at least one embodiment, a method and apparatus for improving the ability to correct errors in memory devices is described. At least one embodiment provides a way to salvage the part even it has double-bit or multi-bit error from the same ECC section, thus improving product reliability and extending the product lifetime. During a normal read, if a double-bit or multiple-bit error happens, which ECC can detect but cannot fix, the error is corrected by adjusting the read voltage level and reading again to determine the proper read level (and, therefore, the correct value being read). This dynamic read scheme can apply to extrinsic bits from either erase state or program state. It can be also used in a single bit scenario to minimize ECC occurrence and save ECC capacity.