Flash Memory Storage Dynamic Reliability Mode Selection

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Solution Overview

Problem

Current flash memory storage systems face challenges in achieving high data reliability while maintaining performance, lifetime, and cost-effectiveness, as they require complex error correction codes and increased write latency, leading to higher costs and limited system lifetime.

Innovation Solution

A storage system with a controller that dynamically adjusts the data reliability by selecting appropriate operation modes based on system information, reducing data retention and increasing the unrecoverable bit error rate when necessary, thereby reducing overhead and improving performance and lifetime.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If complex error correction codes are used to achieve high data reliability, then data reliability is improved, but device complexity and cost increase

Engineering Contradiction:
Improvedata reliabilityVSAvoidECC complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic operation modes that adjust data reliability parameters based on system conditions. The controller can switch between different operation modes (e.g., first mode with higher reliability for critical data, second mode with lower reliability for non-critical data) to optimize the balance between reliability and complexity/cost for different storage scenarios.

Inventive Principle:
Principle #15Dynamics

2Reliability

If strong error correction is implemented to reduce UBER, then data reliability is improved, but write latency increases

Engineering Contradiction:
ImproveUBERVSAvoidwrite latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent changes operational parameters dynamically by adjusting error correction strength based on data importance and system conditions. For less critical data or when performance is prioritized, the system uses weaker error correction (lower UBER protection), thereby reducing write latency while maintaining acceptable reliability levels for different data types.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If high data retention requirements are enforced, then data reliability is improved, but performance and lifetime are degraded

Engineering Contradiction:
Improvedata retentionVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments storage space into different regions or logical units with different retention requirements. Critical data is stored in regions with high retention guarantees, while non-critical data is stored in regions with lower retention requirements, allowing the system to achieve high overall reliability without sacrificing performance for all data equally.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different parts of the storage system are assigned different quality levels of data retention. The controller can designate specific memory blocks, pages, or logical volumes to have enhanced retention characteristics while other areas operate with relaxed retention requirements, optimizing the trade-off between reliability and performance locally.

Inventive Principle:
Principle #3Local quality

4Reliability

If advanced ECC schemes like LDPC are used, then data reliability is improved, but hardware cost and power consumption increase

Engineering Contradiction:
Improvedata reliabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The system dynamically selects error correction schemes based on data criticality and system state. For non-critical data or when power savings are needed, the system uses simpler, lower-power ECC algorithms. For critical data, it activates advanced schemes like LDPC only when necessary, thereby reducing average power consumption while maintaining required reliability levels.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9256526B2Flash memory storage system and access method
Publication Date: 2016.02.09 NAT TAIWAN UNIV
  • US9256526B2 patent drawing
  • US9256526B2 patent drawing
  • US9256526B2 patent drawing

AI summary

The present disclosure relates, according to some embodiments, to a data writing method in a storage system. The method comprises receiving data by the storage media controller, reading a non-volatile memory operation mode in the memory unit by a central control unit, in which the mode corresponds to a data reliability lower than the data reliability requirement of the storage system, reading a data reliability reduction condition in the memory unit by the central control unit, determining whether a system information related to the data meets the condition by the central control unit, and controlling the media control unit to write the data into the non-volatile memory according to the mode by the central control unit when the system information meets the condition.