Modified ECC Algorithm for Flash Memory Erased Page Identification

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Solution Overview

Problem

Existing ECC schemes in NAND-type flash memory devices fail to correctly handle erased pages and intermediate states during the erasure process, leading to incorrect data correction and potential system misinterpretation, especially when power interruptions occur.

Innovation Solution

A modified ECC algorithm that transforms data and parity bits to make all-one codewords legal and all-zero codewords illegal, allowing for correct identification of erased pages and operation errors by inverting bits during computation and storage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If standard ECC schemes are used in NAND-type flash memory, then error detection and correction capability is provided, but erased pages are incorrectly identified as containing errors leading to wrong data correction

Engineering Contradiction:

Improveerror detection and correction capabilityVSAvoiderased page identification accuracy

Core Design Contradiction:

ReliabilityVSMeasurement precision

Solution Approach 1:

The patent inverts the traditional ECC approach by making all-one codewords legal and all-zero codewords illegal. This inversion allows the system to correctly identify erased pages (which contain all-one data bits) as valid states rather than erroneous states. The dual-parity scheme with inverted logic enables the ECC to distinguish between genuinely erased pages and pages with actual errors, resolving the contradiction between maintaining error correction capability and achieving accurate erased page identification.

Inventive Principle:

Principle #13The other way round (Inversion)

2Device complexity

If linear ECC schemes are used, then simple computation is achieved, but symmetrical handling of all-zero and all-one codewords is not provided

Engineering Contradiction:

ImproveECC computation simplicityVSAvoidcodeword symmetry

Core Design Contradiction:

Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent deliberately introduces asymmetry into the ECC system by treating all-zero and all-one codewords differently. Through the use of dual-parity bits and inverted computation logic, the system makes all-one codewords legal while making all-zero codewords illegal. This asymmetric design resolves the contradiction by providing the necessary adaptability to handle erased pages correctly while maintaining relatively simple computation through the structured parity inversion approach.

Inventive Principle:

Principle #4Asymmetry

3Productivity

If erased pages are read during system startup, then memory search can be performed, but incorrect ECC correction may occur on erased pages

Engineering Contradiction:

Improvesystem startup speedVSAvoiddata integrity during memory search

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by pre-configuring the ECC system with inverted parity logic and dual-parity bits before the memory search operation begins. This preparation ensures that when erased pages are encountered during the startup memory search, the ECC algorithm is already configured to correctly identify them as valid erased states rather than erroneous states. This resolves the contradiction by enabling fast memory search while protecting data integrity through pre-established symmetric codeword handling.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS7783955B2Method for implementing error-correction codes in flash memory

Publication Date: 2010.08.24 SANDISK ISRAEL LTD

AI summary

The present invention teaches a method and device for implementing error-correction code (ECC) in flash memory. The present invention discloses methods which utilize a modified ECC algorithm, and a flash memory device which incorporates these methods.