Flash Memory Controller ECC and Arbitrator for Two-Bit Error Correction
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Solution Overview
Problem
Current flash memory technologies face limitations in data access reliability, particularly beyond the erase limit, where data stored in flash memory areas cannot be read due to two-bit errors in multi-level cell (MLC) flash memory, and conventional error correction codes (ECC) are inadequate for correcting errors efficiently without significant hardware changes.
Innovation Solution
An apparatus comprising an encoder, ECC generator, comparator, arbitrator, and decoder improves data access reliability by encoding data, generating ECC, comparing and differentiating voltage levels, and selecting cells to avoid suspicious bits during decoding, thereby enhancing error detection and correction capabilities in MLC flash memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC is used for error correction in flash memory, then one-bit error correction is achieved, but two-bit error correction capability is insufficient
Solution Approach 1:
The flash memory is divided into multiple blocks, and when a penetration error occurs in one block, the system can switch to read from another block. This segmentation allows the system to maintain data accessibility even when individual blocks fail, effectively extending the usable lifespan beyond the conventional erase limit.
Solution Approach 2:
The system pre-maps multiple physical blocks to a single logical address. Before actual data access, the system has already prepared alternative blocks in case of penetration errors. This preliminary preparation enables rapid switching without data loss when errors occur, improving reliability without requiring larger ECC codes.
2Reliability
If the size of reserved area is increased to provide more storage space for ECC, then error correction capability is slightly improved, but system hardware design must be changed which is not economically viable
Solution Approach 1:
Instead of increasing the reserved area for larger ECC codes, the system creates a copy mechanism where multiple blocks are mapped to the same logical address. This copying approach provides equivalent or superior error protection without requiring additional reserved space or hardware redesign, maintaining economic viability while improving reliability.
Solution Approach 2:
The system changes the parameter of block mapping from one-to-one to one-to-many. By modifying this mapping parameter rather than increasing hardware resources, the system achieves improved error correction capability without changing the fundamental hardware design, avoiding the economic burden of system redesign.
3Quantity of substance
If MLC flash memory is used to increase storage capacity, then storage density is improved, but data access reliability deteriorates due to two-bit errors
Solution Approach 1:
The system segments the storage into multiple blocks and implements a blocking mechanism where data is distributed across multiple blocks. When MLC penetration errors occur, the system can switch between blocks to retrieve data, maintaining high reliability despite the inherent vulnerability of MLC to two-bit errors.
Solution Approach 2:
The system introduces a blocking layer as an intermediary between the physical MLC blocks and the logical data access. This intermediary layer manages the complexity of MLC error handling, allowing the system to exploit MLC's high storage density while protecting against its reliability issues through automated block switching and error management.
Data Source
AI summary
An apparatus for improving the data access reliability of flash memory is provided, including an instruction register, an address register, a flash memory control circuit, a data register, an encoder, an error correction code (ECC) generator, a signal converter, a comparator, an arbitrator, and a decoder. The instruction register and the address register are connected to a flash memory respectively for storing the access instructions and the addresses. The flash memory control circuit is connected to both instruction register and address register for controlling the access to the flash memory. The data register is connected to flash memory control circuit for loading data to be written to the flash memory. The encoder encodes the written data, and the ECC generator generates an ECC, which is written to the flash memory through the signal converter. The comparator and the arbitrator provide the comparison with ECC and informing decoder f suspicious bit values when data is read from the flash memory. The decoder is for correctly decoding data and avoiding the suspicious bit values to be read. Thus, the object improving the data access reliability of flash memory is achieved.