Flash Memory ECC Circuit Parallel Error Correction
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Solution Overview
Problem
In NAND flash memory, the ECC processing time is a bottleneck that limits the frequency of the external clock signal during continuous read operations, preventing high-speed reading due to the longer processing time required for multi-bit error detection/correction using BCH codes.
Innovation Solution
The ECC circuit performs error correction by inverting data output from the page buffer/sense circuit to the data bus without accessing the page buffer/sense circuit, allowing parallel processing of error detection and correction, thereby reducing the overall ECC processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC processing is performed by accessing the page buffer/sense circuit to correct errors, then error correction reliability is improved, but processing time increases and reading speed deteriorates
Solution Approach 1:
The patent performs error detection and generates correction information in advance during the data output process. The correction information is prepared beforehand based on read data, and then used for correction without requiring additional access to the page buffer/sense circuit. This preliminary preparation of correction data enables fast correction while maintaining reliability.
Solution Approach 2:
The patent extracts the error correction function from the traditional ECC circuit that requires page buffer access. By implementing correction logic that operates on data already in the output path, it separates the correction function from the buffer access path, eliminating the bottleneck while preserving correction capability.
2Reliability
If multi-bit error detection/correction using BCH codes is implemented, then error correction capability is improved, but processing time increases and external clock frequency is limited
Solution Approach 1:
The patent performs syndrome calculation and correction bit generation in advance during the data output phase. By preparing correction information before final output, it enables complex BCH decoding without extending the critical path that limits external clock frequency.
Solution Approach 2:
The patent segments the ECC processing into independent stages: syndrome calculation, error location determination, and correction bit generation. Each stage operates independently on different data portions, enabling parallel processing that reduces overall processing time and allows higher clock frequencies.
3Productivity
If continuous read operations are performed, then data throughput is improved, but ECC processing becomes a bottleneck that limits operating frequency
Solution Approach 1:
The patent maintains continuous useful action by performing error detection and correction information generation simultaneously with data output operations. The correction process does not interrupt the continuous read flow, allowing uninterrupted high-speed operation across multiple pages.
Solution Approach 2:
Correction information is prepared in advance during the data read and output process, so when continuous read operations proceed to the next page, the correction is already ready. This eliminates waiting time between reads and maintains continuous high-speed operation.
Data Source
AI summary
A semiconductor storing apparatus capable of shortening a ECC processing time of a readout operation is provided, including a flash memory includes: a memory cell array; a page buffer/sense circuit holding data read out from a selected page of the memory cell array; an error correcting code circuit receiving data from the page buffer/sense circuit and holding error address information of the data; an output circuit selecting data from the page buffer/sense circuit based on a column address, and outputting the selected data to a data bus; and an error correction part correcting data of the data bus based on the error address information.