Flash Memory Error Detection Using ECC and CRC Checks
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Solution Overview
Problem
Flash memory devices have limitations in detecting and correcting bit errors, as their error correction code (ECC) circuits can only correct a certain number of errors, leading to reliability issues when more than a specific number of error bits occur.
Innovation Solution
Incorporating a cyclic redundancy check (CRC) circuit that generates and compares CRC codes with ECC codes to detect and correct bit errors, allowing for the detection of multiple error bits beyond the capability of traditional ECC circuits, thereby enhancing the reliability of bit error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If only ECC circuits are used for error correction, then the device complexity is low, but the reliability deteriorates because bit errors beyond the correction capability cannot be detected
Solution Approach 1:
The patent combines ECC and CRC circuits into a unified error detection and correction system. The ECC circuit corrects detectable errors while the CRC circuit detects uncorrectable errors, creating a complementary hybrid system that leverages the strengths of both approaches to improve overall reliability without requiring completely separate systems
Solution Approach 2:
The error detection system is designed to handle multiple types of errors through a single integrated mechanism. The system can detect both correctable errors (via ECC syndrome) and uncorrectable errors (via CRC check), providing universal error detection capability across different error scenarios without requiring separate specialized circuits for each error type
2Device complexity
If the ECC circuit corrects a limited number of bit errors, then the device complexity remains manageable, but the reliability worsens when more error bits occur beyond the correction limit
Solution Approach 1:
The CRC check is performed preliminarily on the received data before attempting ECC correction. This preliminary detection identifies severely corrupted data blocks that should not undergo expensive correction attempts, allowing the system to efficiently handle both small and large error scenarios with appropriate responses
Solution Approach 2:
The CRC circuit acts as an intermediary between the data reception and final validation stages. It provides an additional layer of verification that mediates between the limited ECC correction capability and the need for high reliability, catching errors that exceed ECC's correction capacity without requiring the system to over-engineer the ECC circuits
Data Source
AI summary
A memory device detects and correct bit errors. The memory device includes cyclic redundancy check (CRC) and error correction code (ECC) circuits. The CRC circuit generates a write CRC code corresponding to data to be stored in memory cells. The ECC circuit generates an ECC code corresponding to the data and detecting and correcting a bit error of the data by means of the ECC code during a read operation. The CRC circuit generates a read CRC code corresponding to data corrected by the ECC circuit during the read operation, and detects a bit error of the data according to a comparison of the read CRC code and the write CRC code.