Flash Memory ECC Across Wordline and Finger Dimensions

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Solution Overview

Problem

Conventional flash memory controllers have limited error correction capabilities, particularly for errors occurring in three-dimensional blocks, leading to high data error rates during reading.

Innovation Solution

Implementing a flash memory controller with a buffer and error correction code circuit that performs wordline-dimensional and finger-dimensional error correction operations to generate check codes, correcting errors in super blocks by using distributed RAID mechanisms.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional single-dimension error correction is used, then device complexity is reduced, but error correction capability is insufficient for three-dimensional block errors

Engineering Contradiction:

Improveerror correction capabilityVSAvoiderror correction code circuit complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies two-dimensional error correction by introducing both wordline-dimensional check codes and finger-dimensional check codes. The error correction code circuit performs separate error correction operations in the wordline direction and finger direction, effectively adding a dimensional aspect to error correction that enables correction of three-dimensional block errors that single-dimension correction cannot handle.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If two-dimensional error correction is implemented, then error correction capability is improved, but processing time increases

Engineering Contradiction:

Improvedata accuracyVSAvoiderror correction processing time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The error correction code circuit generates both wordline-dimensional check codes and finger-dimensional check codes during the data writing process, before actual data storage. This preliminary generation of check codes in both dimensions allows for rapid error correction during reading without requiring extensive processing time at the correction stage.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS12487749B2Flash memory controller, operating method of flash memory controller, and storage device capable of performing different dimension error correction to protect data

Publication Date: 2025.12.02 SILICON MOTION INC

AI summary

A flash memory controller, to be coupled between a host device and a flash memory module, includes an error correction code (ECC) circuit. The ECC circuit performs a wordline-dimensional ECC operation upon specific data, sent from the host device to form a super block stored within the flash memory module, to generate wordline-dimensional parity data and performs a finger-dimensional ECC operation upon the specific data generate finger-dimensional parity data. The ECC circuit corrects an error of the superblock by using the wordline-dimensional parity data and the finger-dimensional parity data so as to obtain correct data content of the specific data.