Flash Memory ECC Layout for Word-Line Cut Cell Errors
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Solution Overview
Problem
As semiconductor memory devices, particularly flash memory, are scaled down and memory cells are stacked, their data retention characteristics and error correction capabilities are degraded, leading to increased error occurrence probabilities in outer and inner cells.
Innovation Solution
A storage device with an error correction code (ECC) engine that groups memory cells into outer and inner cells based on their distance from a word-line cut region, performing distinct ECC encoding and decoding operations to enhance error correction capabilities without increasing occupied area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked and fabrication process is scaled-down to increase storage capacity, then storage density is improved, but data retention characteristics and error correction capabilities are degraded
Solution Approach 1:
The patent divides the memory cell array into multiple super pages, where each super page contains multiple pages with different error correction capabilities. This segmentation allows the system to allocate different ECC strengths to different data types, improving overall reliability while maintaining high storage density through the stacked memory cell architecture.
Solution Approach 2:
The patent applies different error correction codes to different regions/pages of the memory array. Specifically, some pages use stronger ECC while others use lighter ECC, matching the error correction capability to the actual error probability of each region. This local differentiation optimizes reliability without uniformly increasing the overhead for all stored data.
2Reliability
If stronger error correction is applied to all memory cells, then error correction capability is improved, but storage efficiency and occupied area are degraded
Solution Approach 1:
The patent segments the error correction approach by creating multiple super pages with different ECC configurations. This allows the system to apply strong error correction only where needed (in pages with higher error probability) while using lighter ECC in other pages, thereby maintaining storage efficiency while improving overall error correction capability.
Solution Approach 2:
The patent changes the ECC parameters dynamically based on the page type and error characteristics. By adjusting the strength of error correction codes applied to different pages within super pages, the system optimizes the balance between error correction capability and storage efficiency, avoiding the overhead of applying maximum ECC strength uniformly across all data.
Data Source
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AI summary
A storage device includes a nonvolatile memory device including a memory cell array and a storage controller to control the nonvolatile memory device. The memory cell array includes word-lines, memory cells and word-line cut regions dividing the word-lines into memory blocks. The storage controller includes an error correction code (ECC) engine including an ECC encoder and a memory interface. The ECC encoder performs a first ECC encoding operation on each of sub data units in user data to generate parity bits and generate a plurality of ECC sectors, selects outer cell bits to be stored in outer cells to constitute an outer ECC sector including the outer cell bits and performs a second ECC encoding operation on the outer ECC sector to generate outer parity bits. The memory interface transmits, to the nonvolatile memory device, a codeword set including the ECC sectors and the outer parity bits.