Flash Memory ECC Staging for Over-Program and Charge Loss
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Solution Overview
Problem
Conventional flash memory devices face challenges in maintaining data integrity due to over-programming and charge loss, leading to increased error correction complexity and hardware requirements, especially in multi-level cell flash memory where threshold voltage offsets cause data access errors.
Innovation Solution
Generating a first error correction code before writing user data and a second error correction code after reading the data, allowing for staged correction using both codes to improve correcting capability without increasing the correctable bit number, thus reducing hardware complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the correctable bit number of the error correction code is continuously increased to correct errors from over-program and charge loss, then the correcting capability is improved, but the hardware complexity and silicon area increase
Solution Approach 1:
The patent divides the error correction process into two separate stages: a first error correction code is generated before writing user data to correct over-program errors, and a second error correction code is generated after reading to correct charge loss errors. This segmentation allows each ECC to handle specific error types with lower correctable bit numbers, reducing hardware complexity while maintaining high correcting capability.
2Reliability
If the correctable bit number of the error correction code is continuously increased to correct errors from over-program and charge loss, then the correcting capability is improved, but the silicon area increases
Solution Approach 1:
The patent segments the error correction function into two distinct codes executed at different times. The first ECC handles over-program errors immediately after writing, while the second ECC handles charge loss errors after reading. This temporal and functional segmentation reduces the required correctable bit number for each individual ECC, thereby reducing the silicon area needed for each error correction circuit.
Solution Approach 2:
The patent applies preliminary error correction by generating the first error correction code before the user data is fully written to the flash memory. This preliminary action corrects over-program errors at the source, preventing them from propagating and reducing the burden on subsequent error correction mechanisms, thus lowering the required silicon area.
3Device complexity
If a single error correction code is used for all errors, then the hardware facility is simpler, but the correcting capability is insufficient for both over-program and charge loss errors
Solution Approach 1:
The patent segments the error correction functionality into two specialized codes: the first ECC is optimized for correcting over-program errors during the writing phase, and the second ECC is optimized for correcting charge loss errors during the reading phase. This segmentation enables each ECC to be simpler in design while collectively providing comprehensive error correction capability.
Solution Approach 2:
The patent changes the operational parameters of error correction by applying different correction codes at different time points and for different error types. The first ECC operates during/after writing with parameters optimized for over-program correction, while the second ECC operates after reading with parameters optimized for charge loss correction, achieving high capability without excessive hardware complexity.
Data Source
AI summary
A method for operating a memory device is provided and includes the following steps. A first error correction code is generated according to user data. Then, the user data is written to the memory device. Moreover, the user data in the memory device is read, and a second error correction code is generated according to the read user data. Further, the first and the second error correction codes are written to the memory device.