Flash Memory ECC Capability Table for Bad Column Management

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Solution Overview

Problem

In flash memory production, the presence of bad columns due to dust or masking issues affects the error correction ability, leading to reduced usable memory space and inefficient error correction capabilities across different memory planes within the same die.

Innovation Solution

A data storage device with a controller that utilizes an ECC capability table to manage and correct data across multiple memory planes within each die, allowing for different ECC capability values for each plane to optimize error correction based on the number of bad columns, thereby optimizing memory space usage and error correction efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional uniform error correction is applied to all memory planes, then implementation is simple, but error correction efficiency deteriorates when different planes have different numbers of bad columns

Engineering Contradiction:
Improveerror correction efficiencyVSAvoidECC management complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by assigning different ECC capability values to different memory planes based on their specific bad column characteristics. Each memory plane is evaluated individually and configured with appropriate ECC parameters, allowing optimal error correction for each plane's actual condition rather than using a uniform approach across all planes.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements dynamics by making the ECC capability configurable and adaptable. The system can dynamically adjust ECC parameters based on the detected bad column distribution, allowing the error correction mechanism to adapt to different memory plane conditions and optimize performance for each specific configuration.

Inventive Principle:
Principle #15Dynamics

2Ease of manufacture

If the number of bad columns is high, then manufacturing defects are tolerated, but error correction ability deteriorates

Engineering Contradiction:
Improvetolerance to manufacturing defectsVSAvoiderror correction ability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies parameter changes by adjusting ECC capability values based on the number of bad columns detected in each memory plane. When high numbers of bad columns are present, the system modifies the ECC parameters to match the actual error correction needs, allowing the system to tolerate manufacturing defects while maintaining appropriate error correction ability for the given conditions.

Inventive Principle:
Principle #35Parameter changes

3Quantity of substance

If uniform ECC capability is assigned to all memory planes, then configuration is simple, but memory space utilization deteriorates

Engineering Contradiction:
Improveusable memory spaceVSAvoidECC configuration complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent applies local quality by configuring each memory plane with its own specific ECC capability value based on its bad column characteristics. This allows each plane to use the minimum necessary ECC overhead for its actual error correction needs, maximizing usable memory space while maintaining appropriate error correction protection for each plane's specific conditions.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS9928137B2Data storage device and error correction method
Publication Date: 2018.03.27 SILICON MOTION INC
  • US9928137B2 patent drawing
  • US9928137B2 patent drawing
  • US9928137B2 patent drawing

AI summary

A data storage device includes a flash memory and a controller. The flash memory includes a plurality of dies, and each of the dies includes a first memory plane and a second memory plane, wherein the first memory plane includes a plurality of pages and the second memory plane includes a plurality of pages. The controller corrects data stored in the first memory plane and the second memory plane according to an ECC capability table, wherein the ECC capability table is arranged to record a first ECC capability value of the first memory plane and a second ECC capability value of the second memory plane.