Flash Memory Dedicated ECC Terminals for Error Correction Speed
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Solution Overview
Problem
In NAND-type flash memory, the narrow bit width of the SPI DO terminal leads to prolonged data transmission times and idle states in the controller chip, hindering the performance of pipeline processing for error detection and correction.
Innovation Solution
The introduction of dedicated terminals for ECC-related data transmission between the NAND chip and the ECC chip, allowing for faster data transfer and reduced idle time during ECC processing, with a wider bit width for the ECC terminal compared to the SPI terminal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the SPI DO terminal with narrow bit width is used for data transmission between NAND chip and controller chip, then the existing interface structure is maintained, but the data transmission time is prolonged and idle states occur in the controller chip
Solution Approach 1:
The interface is segmented into two separate paths: the original SPI interface for general control and communication, and a new dedicated ECC terminal for ECC-related data transmission. This segmentation allows ECC data to be transmitted independently through a wider channel, resolving the bottleneck caused by the narrow SPI DO terminal while maintaining the existing SPI interface structure.
Solution Approach 2:
A dedicated ECC terminal acts as an intermediary channel specifically for ECC data transmission between the NAND chip and controller chip. This intermediary path with wider bit width handles ECC-related data separately from general SPI communication, eliminating the idle states and transmission delays that occurred when ECC data competed for bandwidth on the narrow SPI DO terminal.
2Device complexity
If the SPI DO terminal with narrow bit width is used for data transmission, then the existing interface structure is maintained, but pipeline processing performance is hindered due to prolonged idle states
Solution Approach 1:
The interface is segmented into two separate paths: the original SPI interface for general control and communication, and a new dedicated ECC terminal for ECC-related data transmission. This segmentation allows ECC data to be transmitted independently through a wider channel, resolving the bottleneck caused by the narrow SPI DO terminal while maintaining the existing SPI interface structure.
Solution Approach 2:
The dedicated ECC terminal enables continuous data transmission without the idle states that plagued the SPI interface. By providing a always-available, wider bit width channel for ECC data, the controller chip can maintain continuous pipeline processing operations, eliminating interruptions and maximizing productivity.
3Loss of time
If a dedicated terminal with wider bit width is introduced for ECC data transmission, then data transmission time is shortened and pipeline processing is optimized, but the device structure becomes more complex
Solution Approach 1:
The dedicated ECC terminal is designed with multi-functionality, serving both as a high-speed data transmission channel and as a specialized interface for ECC operations. This universal terminal handles multiple ECC-related tasks (data transmission, parity transmission, status signaling) through a single wider bit width interface, reducing the need for multiple separate specialized components and minimizing overall device complexity.
4Productivity
If a dedicated terminal with wider bit width is introduced for ECC data transmission, then pipeline processing efficiency is optimized, but the number of terminals increases
Solution Approach 1:
The dedicated ECC terminal is designed with multi-functionality, serving both as a high-speed data transmission channel and as a specialized interface for ECC operations. This universal terminal handles multiple ECC-related tasks (data transmission, parity transmission, status signaling) through a single wider bit width interface, reducing the need for multiple separate specialized components and minimizing overall device complexity.
Data Source
AI summary
The disclosure provides a semiconductor storage device, which can shorten the processing time for error detection and correction. The flash memory of the present disclosure has a NAND chip and an ECC chip. The NAND chip has dedicated input and output terminals which can transmit data with the ECC chip, and the ECC chip has a dedicated input and output terminal which can transmit data with the NAND chip. When reading in the NAND chip, the NAND chip transmits the read data containing the parity data to the ECC chip through the dedicated input and output terminals. The ECC chip detect and correct errors in the read data based on the parity data, and the corrected data is transmitted to the controller through the input and output terminals.