Flash Memory ECC Layout for Sector-Free Bit Updates
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Solution Overview
Problem
Flash memory devices face inefficiencies in error correction, requiring the rewriting of entire sectors for simple bit changes due to the need to update error correction bits, which is slow and complex, especially in applications demanding high reliability like automotive and medical uses.
Innovation Solution
Implementing a data storage system with additional sets of error correction bits and a method to determine the correct set for updating, allowing for selective updating and reducing the need for rewriting entire sectors by using flag bits and multiple error correction bit sets to manage error correction codes efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction bits are added to every word in flash memory, then reliability against errors is improved, but the complexity of updating data worsens because entire sectors must be rewritten for simple bit changes
Solution Approach 1:
The patent divides the error correction mechanism into two independent parts: a first set of error correction bits stored with the data, and a second set of error correction bits stored separately in a status register. This segmentation allows the data area to be updated without requiring updates to all error correction bits, as the second set can be independently managed and selected based on validation flags.
Solution Approach 2:
The patent introduces a status register as an intermediary structure that stores the second set of error correction bits and validation flags. This intermediary acts as a buffer between the data storage area and the error correction mechanism, allowing selective validation and updating without requiring full sector rewrites. The status register mediates the error correction process by holding alternative correction data that can be applied without modifying the original data sector.
2Reliability
If error correction bits are updated for every bit change, then data integrity is improved, but the writing speed worsens due to the slow erase and rewrite process
Solution Approach 1:
The patent performs preliminary error correction bit generation and stores the second set of error correction bits in the status register before actual data updates are needed. Validation flags are set in advance to indicate which error correction set is current. This preliminary action allows future data updates to proceed without requiring recalculation and rewriting of error correction bits, significantly improving writing speed while maintaining data integrity.
Solution Approach 2:
The patent implements a mechanism where old error correction bits are discarded and replaced by a second set stored in the status register when updates occur. The validation flag system allows the system to recover and use the appropriate error correction set without requiring physical rewriting of the data sector. This discarding and recovering approach eliminates the slow erase-rewrite cycle while preserving error correction capability.
3Productivity
If multiple sets of error correction bits are implemented, then the ability to handle updates without full sector rewrites is improved, but the memory space requirement worsens
Solution Approach 1:
The patent applies local quality by placing the second set of error correction bits and validation flags only in the status register area, rather than duplicating error correction mechanisms throughout the entire data storage area. This localized approach provides the benefits of multiple error correction sets for efficient updates while consuming minimal additional memory space, as the redundant error correction data is confined to a small status register rather than being distributed across the whole memory array.
Data Source
AI summary
A method of enhancing error correction in a data storage system, including receiving a data storage system having one or more rows each row having: a set of data bits including a word of data, a first set of error correction bits and a second set of error correction bits or a flag bit or both; each bit can be in a first state or a second state; wherein initially all the bits are in the first state; writing data in a word in the data storage system by changing bits from the first state to the second state; creating an error correction code for the word and writing it to the first set of error correction bits; when needing to update the word using the second set of error correction bits and/or the flag bit to reduce the need to rewrite the word because of the error correction code.