Flash Memory ECC Allocation for Page Capacity
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Solution Overview
Problem
Previous flash memory systems are inefficient in utilizing page capacity and allocating error correction codes (ECCs) due to fixed ECC bit length and page size, leading to high overhead consumption and limited reliability and performance.
Innovation Solution
A flash memory system with pages partitioned into multiple memory zones of varying or identical sizes, utilizing multiple ECC engines with varying bit lengths and algorithms like Hamming, Reed-Solomon, and BCH codes, where ECCs with longer bit lengths are applied to areas with high error recurrence, and an ECC judgment unit selects the appropriate ECC based on memory zones and data characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If fixed ECC bit length and page size are used according to industry standard, then device complexity is reduced and ease of manufacture is improved, but page capacity utilization becomes inefficient and error correction overhead increases
Solution Approach 1:
The patent implements dynamic ECC allocation where the ECC bit length is not fixed but adapts based on the actual data size stored in each page. The system divides pages into multiple memory zones and dynamically selects appropriate ECC engines (with different bit lengths like 8-bit, 16-bit, 24-bit) based on the data characteristics and error recurrence patterns of each zone, thereby improving page capacity utilization without excessive complexity
Solution Approach 2:
The system changes the parameter of ECC bit length from a fixed industry standard value to a variable parameter that can be adjusted according to actual needs. By implementing multiple ECC engines with different bit lengths and selecting the appropriate one based on data characteristics, the system optimizes the balance between error correction capability and storage efficiency
2Reliability
If longer ECC bit length is used to improve error correction capability in high error recurrence areas, then reliability is improved, but error correction overhead and device complexity increase
Solution Approach 1:
The patent applies different ECC bit lengths to different memory zones based on their error recurrence characteristics. High error recurrence zones use longer ECC bit lengths (e.g., 24-bit) for better protection, while low error recurrence zones use shorter ECC bit lengths (e.g., 8-bit), thereby achieving reliable error correction where needed without unnecessarily increasing complexity and overhead in all areas
Solution Approach 2:
The system segments each page into multiple memory zones and applies different ECC strategies to each zone independently. This segmentation allows the system to manage complexity by handling each zone with an appropriate ECC level rather than applying a uniform complex ECC scheme to the entire page
3Device complexity
If uniform ECC allocation is applied to all memory zones, then device complexity is reduced, but efficiency in utilizing page capacity and error correction performance deteriorate
Solution Approach 1:
The system changes from uniform ECC allocation to variable ECC allocation by implementing multiple ECC engines with different bit lengths and selecting the appropriate engine based on data characteristics and zone error patterns, thereby improving error correction efficiency without excessive complexity
Solution Approach 2:
The patent implements dynamic selection of ECC engines based on runtime conditions such as data characteristics and error recurrence patterns. The ECC judgment unit dynamically determines which ECC engine to use for each memory zone, achieving efficient error correction adaptation without requiring overly complex static design
Data Source
AI summary
A flash memory system comprises a group of pages each consisting of a plurality of memory zones with various sizes; a read/write controller for controlling reading or writing of data from or to one of the pages; an error correction unit including at least two ECC (Error Correction Code) engines each encoding or decoding the data for performing error detection and correction; and an ECC judgment unit for selecting one of the ECC engines on the basis of predetermined conditions.