Flash Memory Fabrication via Embedded Doped Regions
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Solution Overview
Problem
The challenge in fabricating flash memory devices is the high cost and complexity of photomasks due to the need for complex optical proximity correction, which results in non-uniformity and increased sheet resistance of source rails and contacts.
Innovation Solution
A method of fabricating memory devices that forms self-align trenches and embedded doped regions using a mask layer with intersecting openings, allowing for ion implantation without complex optical proximity correction, thereby reducing sheet resistance and integrating with existing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source rails and source contacts are fabricated with larger sizes to reduce sheet resistance, then sheet resistance is reduced, but photomask complexity and cost increase significantly
Solution Approach 1:
The patent introduces a third dimension by forming embedded doped regions that extend vertically into the substrate. This vertical extension creates additional conductive pathways that reduce sheet resistance without requiring larger lateral dimensions of source rails, thereby avoiding photomask complexity while achieving the electrical performance goal
Solution Approach 2:
The patent embeds doped regions within the substrate structure, nesting the conductive elements inside the existing device architecture. The embedded doped regions are positioned between the source rails and the substrate, creating a nested configuration that provides additional conduction paths without increasing the lateral footprint or requiring complex photomask designs
2Reliability
If source rails and source contacts are fabricated with larger sizes to reduce sheet resistance, then sheet resistance is reduced, but manufacturing uniformity deteriorates
Solution Approach 1:
By transitioning from a two-dimensional lateral expansion to a three-dimensional structure with vertical embedding, the patent achieves reduced sheet resistance through increased conductive volume rather than increased lateral area. This approach maintains consistent lateral dimensions across the wafer, improving manufacturing uniformity while achieving the electrical performance target
Solution Approach 2:
The embedded doped regions are formed during the fabrication process before final source rail formation. This preliminary action of creating the embedded conductive pathways early in the process ensures uniformity is established before subsequent processing steps, reducing variability in the final sheet resistance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the sheet resistance of source rails and contacts, simplifies the photomask design, and integrates with existing processes, reducing manufacturing costs and improving uniformity.
Implementation Method 1
An ion implantation process is performed by using the mask layer as an implanting mask, so as to form a first embedded doped region and a second embedded doped region
Data Source
AI summary
Provided is a method of fabricating a memory device including performing an ion implantation process by using a mask layer as an implanting mask, so as to form a first embedded doped region and a second embedded doped region in a substrate. The first embedded doped region extends along the first direction, passes through the control gate, and is electrically connected to the first doped region, the second doped region and the third doped region at two sides of control gates. The second embedded doped region extends along the second direction, is located in the substrate under the third doped region, and electrically connected to the third doped region. The first embedded doped region is electrically connected to the second embedded doped region.