Flash Memory Endurance via Shaped Data Transformation
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Solution Overview
Problem
Flash memory devices face limited endurance due to Write/Erase cycles, leading to reduced data retention and increased failure rates, especially in compressible data storage scenarios, where existing compression and encoding methods introduce latency and power consumption issues.
Innovation Solution
The implementation of Static Shaping Transformation (SST) and Adaptive Shaping Transformation (AST) methods, which transform input data into 'shaped' data by mapping sub-strings to reduce the distribution of high threshold voltage usage, thereby enhancing endurance and retention without the need for initial compression, thus reducing latency and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If compression and encoding are performed in a data storage device, then memory wear is reduced, but latency increases and power consumption increases
Solution Approach 1:
The patent applies preliminary action by pre-computing and storing mapping tables that define the transformation from input data patterns to optimized output patterns. This allows the encoding to be performed simply by table lookup during write operations, rather than performing complex compression and encoding algorithms in real-time, thus reducing latency while still achieving memory wear reduction
Solution Approach 2:
The patent introduces an intermediary transformation layer that maps input data patterns to output patterns with favorable voltage distributions. This intermediary mapping table acts as a mediator between the raw data and the memory cells, enabling wear reduction without requiring full compression/encoding processing, thus balancing endurance improvement with acceptable write latency
2Reliability
If compression and encoding are performed in a data storage device, then memory wear is reduced, but power consumption increases
Solution Approach 1:
The patent performs the computationally intensive transformation logic in advance by pre-computing mapping tables during device initialization or manufacturing. During actual write operations, only simple table lookups and pattern substitutions are needed, dramatically reducing power consumption compared to real-time compression and encoding while still achieving memory wear reduction through optimized voltage distribution
3Reliability
If compression and encoding are performed in a data storage device, then memory wear is reduced, but manufacturing cost increases
Solution Approach 1:
The patent moves the complex processing logic to the software/firmware domain by pre-computing mapping tables, eliminating the need for additional hardware encoding/decoding circuits. This software-based approach reduces manufacturing complexity and cost while still providing memory wear reduction through intelligent data transformation
Solution Approach 2:
The patent replaces potential hardware encoding/decoding circuitry with a software-based transformation approach using pre-computed lookup tables. This substitution of mechanical/electronic hardware with software logic simplifies the device architecture, reduces manufacturing cost, and maintains the ability to reduce memory wear through optimized data patterns
Data Source
AI summary
Methods described in the present disclosure may be based on a direct transformation of original data to “shaped” data. In a particular example, a method comprises generating a first portion of output data by applying a mapping of input bit sequences to output bit sequences to a first portion of input data, updating the mapping of the input bit sequences to the output bit sequences based on the first portion of the input data to generate an updated mapping, reading a second portion of the input data, and generating a second portion of the output data by applying the updated mapping of the input bit sequences to the output bit sequences to the second portion of the input data.