Flash Memory EPI Timing for Threshold Voltage Reliability
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Solution Overview
Problem
Flash memory devices experience reliability issues due to fluctuations in threshold voltages of memory cells, leading to data loss and reduced performance, which conventional controllers struggle to manage effectively.
Innovation Solution
The memory device includes an EPI timer and table to measure and manage erase to program interval (EPI) times, providing EPI information to the controller when the time exceeds a reference, allowing the controller to perform appropriate operations to maintain reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If flash memory devices store data by controlling threshold voltages of memory cells, then data storage capacity is improved, but threshold voltage fluctuations occur leading to reading errors and reduced reliability
Solution Approach 1:
The patent implements a feedback mechanism where the memory device monitors EPI time and provides EPI information to the controller when the time exceeds a reference threshold. This feedback loop enables the controller to adjust program operations accordingly, compensating for threshold voltage fluctuations and maintaining data reliability without sacrificing storage capacity.
2Ease of operation
If conventional controllers manage flash memory operations, then basic storage functions are achieved, but controllers lack sufficient resources or management capabilities to effectively handle threshold voltage fluctuations
Solution Approach 1:
The memory device performs self-monitoring and self-reporting of EPI time conditions to the controller. By embedding the timing measurement and status indication functionality within the memory device itself, the system eliminates the need for complex controller-based monitoring, maintaining operational simplicity while improving reliability through accurate EPI tracking.
3Reliability
If the memory device manages EPI time and provides EPI information to the controller, then reliability is improved through timely program or close operations, but device complexity increases due to additional timing management components
Solution Approach 1:
The patent segments the EPI management function by separating timing measurement and status indication from the controller's responsibilities. The memory device independently manages EPI timing and only communicates necessary status information to the controller, reducing the complexity burden on the controller while maintaining reliable program operation management.
Data Source
AI summary
A memory device including: a memory cell array including a first memory block; a control logic circuit configured to receive an erase command from an external controller and to control an erase operation on the first memory block in response to the erase command; an erase to program interval (EPI) timer configured to begin measuring a first EPI time of the first memory block in response to the erase command; and a memory circuit configured to store an EPI table that stores the first EPI time, wherein, when the first EPI time exceeds a reference time, the control logic circuit is further configured to provide EPI information to the external controller.