Flash Memory EPI Tracking for Data Retention Reliability
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Solution Overview
Problem
Flash memory devices experience reliability issues due to fluctuations in threshold voltages of memory cells, leading to data loss and decreased performance, which conventional controllers struggle to manage effectively.
Innovation Solution
The memory device includes an EPI timer and table to measure and manage erase to program interval (EPI) times, providing EPI information to the controller when the time exceeds a reference, allowing the controller to perform appropriate operations on memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the controller manages EPI time for all memory blocks, then reliability improves, but device complexity and resource requirements increase
Solution Approach 1:
The patent divides the EPI time management function into two segments: the memory device manages EPI time for individual memory blocks using local timers and status flags, while the controller only receives status information and makes high-level decisions. This segmentation reduces controller complexity while maintaining reliability through distributed time tracking.
Solution Approach 2:
The patent introduces an intermediary status flag mechanism where the memory device sets internal status flags when EPI time exceeds thresholds, and the controller queries these flags through status registers. This intermediary layer allows the controller to manage EPI time without directly implementing complex timing logic, reducing its resource requirements.
2Reliability
If the controller has full EPI time management capability, then data retention improves, but resource consumption increases
Solution Approach 1:
The memory device performs self-service by autonomously tracking EPI time using internal timers and automatically setting status flags when thresholds are exceeded. This eliminates the need for the controller to continuously monitor and manage EPI time, reducing controller energy consumption while maintaining data retention reliability.
Solution Approach 2:
The memory device performs preliminary action by pre-calculating and pre-setting status flags based on EPI time thresholds before the controller needs to make decisions. This allows the controller to simply query status registers rather than implementing complex timing logic, significantly reducing its resource and energy requirements.
3Device complexity
If EPI time is not monitored, then device complexity reduces, but threshold voltage fluctuations cause errors
Solution Approach 1:
The patent implements feedback by having the memory device continuously monitor EPI time and automatically set status flags when thresholds are exceeded. The controller queries these status flags to determine appropriate actions, creating a closed-loop feedback system that ensures reliable data reading without requiring complex controller-side time management.
Solution Approach 2:
The patent replaces the mechanical/system-level complexity of EPI time management with a simpler status flag mechanism. Instead of the controller implementing complex timing logic and monitoring, the system uses predefined status flags that automatically indicate when EPI time thresholds are exceeded, substituting complex control mechanics with simpler status indication.
Data Source
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AI summary
A memory device including: a memory cell array including a first memory block; a control logic circuit configured to receive an erase command from an external controller and to control an erase operation on the first memory block in response to the erase command; an erase to program interval (EPI) timer configured to begin measuring a first EPI time of the first memory block in response to the erase command; and a memory circuit configured to store an EPI table that stores the first EPI time, wherein, when the first EPI time exceeds a reference time, the control logic circuit is further configured to provide EPI information to the external controller.