Flash Memory Erase Control via Current Sensing and Soft-Program Verification
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Solution Overview
Problem
Conventional current-type sensing circuits in flash memory face challenges in accurately controlling threshold voltages during programming and erasure due to variations in memory cell size and tunnel oxide layer deterioration, leading to uneven erasure and increased power consumption.
Innovation Solution
A semiconductor memory apparatus with a current-type sensing circuit that employs an erase sequence and a soft-program sequence, including erase verification and soft-program verification, to control the current flow and apply specific voltages to word lines, ensuring accurate erasure and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional current-type sensing circuits are used in flash memory, then high-speed operation is achieved, but power consumption increases due to over-erasure of memory cells
Solution Approach 1:
The patent segments the memory array into multiple blocks, each with its own sensing circuit. This allows independent sensing and control of current in each block, enabling precise detection of memory cell states without requiring high current levels across the entire array, thus reducing overall power consumption while maintaining high-speed operation capability
Solution Approach 2:
The patent implements local sensing circuits for each block that can independently detect and control current flow. This local quality approach allows the system to apply sensing and control operations only to specific blocks where data needs to be read or erased, rather than activating the entire array, thereby reducing power consumption while preserving high-speed performance
2Adaptability or versatility
If memory cell size and tunnel oxide layer vary during manufacturing, then manufacturing flexibility is improved, but threshold voltage control precision deteriorates
Solution Approach 1:
The patent incorporates sensing circuits that provide feedback on the actual current flow and threshold voltage states of memory cells. This feedback mechanism allows the control system to detect deviations from expected threshold voltages and adjust programming/erasure operations accordingly, compensating for manufacturing variations and achieving precise threshold voltage control despite process variations
Solution Approach 2:
The patent dynamically adjusts programming and erasure parameters (voltage levels, pulse widths) based on real-time sensing feedback. By changing these parameters adaptively during operations, the system can compensate for manufacturing variations in memory cell size and tunnel oxide layer, maintaining precise threshold voltage control across diverse device characteristics
3Measurement precision
If erase verification is performed on all memory cells, then erasure accuracy is improved, but processing time increases
Solution Approach 1:
The patent divides the memory array into multiple blocks with independent sensing circuits, enabling parallel erasure verification across different blocks. This segmentation allows simultaneous verification operations in multiple blocks, maintaining high erasure accuracy while significantly reducing total processing time compared to sequential verification of all cells
Solution Approach 2:
The patent performs preliminary sensing and verification operations during the programming/erasure process itself, rather than requiring separate post-processing verification steps. By integrating verification into the operational sequence and performing preliminary checks, the system achieves accurate erasure verification without adding significant processing time
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high-speed operation and reduced power consumption by effectively controlling the threshold voltages of memory cells, minimizing over-erasure and optimizing current flow, thereby improving the efficiency of data reading and writing processes.
Implementation Method 1
A current-type sensing circuit electrically connected with each bit line of the memory array for sensing the current of a selected bit line
Implementation Method 2
an erase unit for erasing data in the memory cells of the selected block of the memory array
Implementation Method 3
a soft-program sequence that includes a soft-program verification that applies a soft-program voltage to all the word lines in the erased block and determines whether the current of each bit line is lower than a second value
Data Source
AI summary
A flash memory with low power consumption and rapid operations is disclosed, including a memory array of memory cells, a word line selection circuit for selecting a row of cells, a current-type sensing circuit electrically connected with each bit line for sensing the current of a selected bit line, and an erase unit erasing the cells in a selected block of the array. The erase unit includes: an erase sequence that determines whether the current of each bit line in the erased block is larger than a first value and ends the erasure if the result is “yes”, and a soft-program sequence that performs a soft program verification, which applies a soft-program voltage to all word lines in the erased block and determines whether the current of each bit line is lower than a second value, and ends the soft programming if the result is “yes”.