Flash Memory Erase Depth Control via Cell Grouping

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Solution Overview

Problem

As storage density increases in data storage devices like flash memory, variations in erase speed and duration among cells become more pronounced due to factors such as cell damage, charge leakage, and manufacturing differences, leading to inconsistent data retrieval and storage reliability.

Innovation Solution

Implementing an erase depth control system that uses different voltage profiles for different sets of storage cells within a block, determining the erase speed and duration based on verify voltage thresholds to ensure consistent and efficient erasure, thereby compensating for variations in cell performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single erase operation is applied to all storage cells in a block, then the erase operation is simple and fast, but cells with different erase speeds result in inconsistent erasure and reduced reliability

Engineering Contradiction:
Improveerase consistencyVSAvoiderase control complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides storage cells into multiple groups based on their erase speeds. A controller performs separate erase operations on different groups of cells, where each group is identified by its erase speed characteristics. This segmentation allows tailored erase parameters for each group, ensuring consistent erasure across all cells while managing complexity through systematic organization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different erase parameters to different groups of storage cells based on their individual erase speed characteristics. Instead of uniform treatment, each group receives customized voltage profiles and timing parameters appropriate to its erase speed, thereby achieving locally optimized erasure quality that contributes to overall reliability.

Inventive Principle:
Principle #3Local quality

2Reliability

If different voltage profiles are applied to different sets of cells to match erase speeds, then erase consistency and reliability improve, but the complexity of controlling and managing multiple voltage profiles increases

Engineering Contradiction:
Improvedata integrityVSAvoidvoltage control complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic voltage control where the controller adapts voltage profiles based on real-time or pre-characterized erase speed data of different cell groups. The system dynamically selects and applies appropriate voltage parameters for each group during erase operations, enabling reliable erasure while managing control complexity through automated adaptation rather than static fixed parameters.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent employs feedback mechanisms where the controller monitors erase progress or uses pre-stored erase speed characteristics to determine appropriate voltage profiles for different cell groups. This feedback loop enables the system to adjust voltage parameters based on actual or historical performance data, ensuring data integrity while automating the control process to manage complexity.

Inventive Principle:
Principle #23Feedback

3Reliability

If erase speed variations among cells are ignored, then the control process remains simple, but cell degradation increases and storage reliability decreases

Engineering Contradiction:
Improvestorage reliabilityVSAvoiderase operation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary characterization or identification of cell groups based on their erase speeds before the main erase operation. This preliminary sorting or grouping allows the controller to prepare and apply optimized voltage profiles in advance for each group, preventing unnecessary cell degradation from mismatched parameters while streamlining the overall erase process to minimize time loss.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10304551B2Erase speed based word line control
Publication Date: 2019.05.28 SANDISK TECHNOLOGIES LLC
  • US10304551B2 patent drawing
  • US10304551B2 patent drawing
  • US10304551B2 patent drawing

AI summary

Apparatuses, systems, methods, and computer program products are disclosed for erase depth control. One apparatus includes a block of non-volatile storage cells. A controller is configured to perform a first erase operation on a block of non-volatile storage cells. A controller for a block is configured to determine a first set of storage cells of the block having a faster erase speed than a second set of storage cells of the block based on a verify voltage threshold. A controller for a block is configured to perform a second erase operation on the block using different voltages for a first set of storage cells and a second set of storage cells of the block.