Flash Memory Secure Erase via Hidden Intermediate States

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Solution Overview

Problem

Current erase operations in computing systems do not physically remove data from memory, leaving it potentially recoverable, and existing secure erase procedures are slower and reduce memory device endurance.

Innovation Solution

Implementing hidden states within the memory device that can only be accessed internally, allowing memory cells to be programmed to an undefined intermediate state that destroys previous data traces, ensuring secure erasure without external intervention.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of information

If traditional erase operations are performed on memory devices, then the memory appears erased to external systems, but the data remains physically present and potentially recoverable

Engineering Contradiction:

Improvedata securityVSAvoiddata recoverability

Core Design Contradiction:

Loss of informationVSReliability

Solution Approach 1:

The patent segments the memory erase process into two distinct phases: a first erase operation that prepares the memory for erasure, and a second erase operation that actually destroys the data. This segmentation allows the system to achieve secure erasure by ensuring that no readable data remains after the second erase operation, while maintaining compatibility with external systems during the process.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies preliminary action by performing the first erase operation before the second erase operation. The first erase operation prepares the memory device by clearing data in a manner that facilitates the subsequent second erase operation, which then permanently destroys the data. This preliminary action ensures that when the second erase occurs, the data is already in a state that makes it impossible to recover.

Inventive Principle:

Principle #10Preliminary action

2Loss of information

If secure erase procedures are implemented to physically remove data, then data security is improved, but erase operation speed decreases

Engineering Contradiction:

Improvedata securityVSAvoiderase operation speed

Core Design Contradiction:

Loss of informationVSProductivity

Solution Approach 1:

The patent maintains continuity of useful action by implementing a seamless two-stage erase process where the first and second erase operations occur in continuous sequence without interruption. The memory device transitions smoothly from the first erase state to the second erase state, ensuring that the secure erasure process completes efficiently without unnecessary delays or interruptions that would reduce productivity.

Inventive Principle:

Principle #20Continuity of useful action

3Loss of information

If secure erase procedures are implemented to physically remove data, then data security is improved, but memory device endurance is reduced

Engineering Contradiction:

Improvedata securityVSAvoidmemory device endurance

Core Design Contradiction:

Loss of informationVSDuration of action of stationary object

Solution Approach 1:

The patent applies parameter changes by modifying the erase operation parameters in two distinct stages. The first erase operation uses specific voltage and timing parameters that prepare the memory cells for erasure, while the second erase operation uses different parameters that permanently destroy the data. By optimizing these parameters for each stage, the patent achieves secure erasure while minimizing the stress on memory cells and preserving device endurance.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS8296508B1Secure memory device erase

Publication Date: 2012.10.23 MICRON TECHNOLOGY INC

AI summary

Subject matter disclosed herein relates to an erasable memory device, and more particularly to a securely erasable flash memory device.