Flash Memory Erase Pulse Rise Time Control

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Solution Overview

Problem

NAND-type flash memory experiences progressive degradation of tunnel insulation films due to repeated program and erase operations, leading to reduced reliability and shorter memory cell lifespan, primarily because of the stress caused by voltage applications during these operations.

Innovation Solution

A non-volatile semiconductor storage device with a control unit that applies an erase pulse voltage with a longer rise time initially and subsequently increases the voltage in stages if the erase is not complete, reducing the stress on memory cells by controlling the waveform of the erase pulse voltage to mitigate degradation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high erase voltage is applied to complete data erase, then erase effectiveness is improved, but stress on tunnel insulation film increases leading to degradation

Engineering Contradiction:

Improveerase effectivenessVSAvoidstress on tunnel insulation film

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies periodic erase pulse voltages with controlled rise times instead of continuous high voltage. By using multiple erase pulses with alternating application to different bit line groups, the system achieves complete erase while allowing stress distribution and recovery periods for the tunnel insulation film.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The patent applies a first erase pulse voltage with a longer rise time before applying subsequent erase pulses with shorter rise times. This preliminary action with a gentler voltage transition prepares the tunnel insulation film for subsequent higher stress pulses, reducing cumulative damage while ensuring complete erase.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If multiple iterations of erase and verify operations are performed, then data erase completeness is improved, but cumulative stress on memory cells increases

Engineering Contradiction:

Improvedata erase completenessVSAvoidmemory cell lifespan

Core Design Contradiction:

ReliabilityVSDuration of action of stationary object

Solution Approach 1:

The patent divides the memory cell array into multiple groups based on bit line connections and applies erase pulses selectively to different groups in sequence. This segmentation allows the system to achieve complete erase across all cells while distributing the cumulative stress across multiple shorter exposure periods rather than one prolonged high-stress operation.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary erase operations with controlled rise times before conducting verify operations. By establishing proper voltage conditions in advance with gentler rise times, the system reduces the need for repeated high-stress erase cycles, thereby extending memory cell lifespan while ensuring erase completeness.

Inventive Principle:

Principle #10Preliminary action

3Productivity

If erase pulse voltage with short rise time is used, then erase speed is improved, but tunnel insulation film degradation accelerates

Engineering Contradiction:

Improveerase speedVSAvoidtunnel insulation film degradation

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent alternates between erase pulses with different rise times applied to different bit line groups. This periodic action allows the system to maintain high overall erase speed while periodically reducing stress on the tunnel insulation film through longer rise time pulses, preventing cumulative degradation.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The patent applies a preliminary erase pulse with a longer rise time before subsequent faster erase pulses. This preliminary action with a gentler voltage transition prepares the tunnel insulation film for faster subsequent pulses, enabling high-speed erase operations without accelerating film degradation.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the stress on tunnel insulation films, improving the reliability and extending the lifespan of memory cells by ensuring a gradual discharge of electric charges during the erase operation, thereby minimizing incorrect programming and enhancing data retention.

Implementation Method 1

data program and erase are performed in NAND-type flash memory by causing FN tunnel current to flow through many cells at the same time

Methodology Applied

Scientific EffectFowler-Nordheim tunneling:

Data Source

PatentUS9928915B2Non-volatile semiconductor storage device

Publication Date: 2018.03.27 KIOXIA CORP

AI summary

For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage.