Flash Memory Erase Scheduling During Variable Word Line Writes
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Solution Overview
Problem
Flash memory devices face challenges in maintaining consistent quality of service (QoS) due to varying data write times across word lines within blocks, leading to inefficient data erasing operations.
Innovation Solution
A storage device with a splitter that determines a reference time based on the longest write time for word lines and schedules erase operations during the remaining time, allowing for efficient data erasing by dividing and distributing these operations across blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the flash memory device allocates the same time for quality of service (QoS) to all word lines, then QoS consistency is maintained, but data write time varies causing inefficient data erasing operations
Solution Approach 1:
The patent performs data erasing operations in advance during the remaining time of write operations. The controller identifies word lines that have completed writing earlier than the reference time and immediately initiates erasing operations on other blocks during this remaining time, rather than waiting for all write operations to complete before starting erasing.
Solution Approach 2:
The patent ensures continuous utilization of the flash memory device by overlapping write and erase operations. While some word lines are completing write operations, the controller simultaneously performs erasing operations on other blocks, eliminating idle time and maintaining continuous productive action throughout the reference time period.
2Manufacturing precision
If data erasing operations are performed after data writing completes, then write operations are completed accurately, but overall operation time increases due to sequential processing
Solution Approach 1:
The patent performs data erasing operations in advance during the remaining time of write operations. The controller identifies word lines that have completed writing earlier than the reference time and immediately initiates erasing operations on other blocks during this remaining time, rather than waiting for all write operations to complete before starting erasing.
Solution Approach 2:
The patent transitions from sequential processing (one operation after another) to parallel processing by executing write operations on one block and erasing operations on another block simultaneously. This dimensional change in processing approach allows both operations to occur in overlapping time periods rather than strictly sequentially.
3Reliability
If the flash memory device waits for the longest write time before performing erase operations, then all write operations complete successfully, but input/output latency increases
Solution Approach 1:
The patent performs data erasing operations in advance during the remaining time of write operations. The controller identifies word lines that have completed writing earlier than the reference time and immediately initiates erasing operations on other blocks during this remaining time, rather than waiting for all write operations to complete before starting erasing.
Solution Approach 2:
The controller acts as an intermediary that manages multiple operations simultaneously. It monitors write operation progress, identifies completed word lines, and coordinates erasing operations on other blocks during the remaining time, effectively mediating between write and erase operations to minimize latency while ensuring completion.
Data Source
AI summary
A storage device includes: a non-volatile memory configured to include a plurality of blocks having a plurality of word lines and to write data to the blocks or to erase data of the blocks; and a splitter configured to obtain write times for a plurality of word lines of a first block of the blocks while the non-volatile memory writes data in the first block, and to command the non-volatile memory to perform an erase operation on a second block of the blocks by the reference time when a write time for one of the word lines is shorter than the reference time.