Flash Memory Erase Method Using Substrate Pre-Charge and Floating Gate

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Solution Overview

Problem

The existing methods for erasing flash memory cells are inefficient due to uncertainty in determining the start time of the erase operation, leading to potential over- or under-erasure, and require significant time and power for charging and discharging voltages, especially when dealing with dummy cells.

Innovation Solution

A method and system that involve coupling the substrate to a first voltage to increase its level, floating the control gate to match the substrate voltage, and then coupling the control gate to a second voltage via the word line to discharge charges on the isolated carrier storage layer for erasure, while maintaining a voltage level on dummy cells to prevent over-erasure and optimizing voltage control for efficient erasure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the erase voltage is increased to ensure complete erasure, then the erasing operation reliability is improved, but the power consumption and time required for voltage charging and discharging increase

Engineering Contradiction:

Improveerasing operation reliabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies preliminary action by pre-charging the substrate to a first voltage level before initiating the erase operation. This preparation ensures that when the erase voltage is applied, the timing is precise and controlled, eliminating the need for repeated voltage charging cycles and reducing overall power consumption while maintaining reliable erasure.

Inventive Principle:

Principle #10Preliminary action

2Manufacturing precision

If the erase operation timing is delayed to ensure complete voltage charging, then the manufacturing precision is improved, but the productivity decreases due to extended operation time

Engineering Contradiction:

Improveerase timing precisionVSAvoiderase operation speed

Core Design Contradiction:

Manufacturing precisionVSProductivity

Solution Approach 1:

The substrate is pre-charged to the first voltage level before the erase operation begins. This preliminary voltage establishment enables precise timing control at the moment of erasure, achieving both accurate timing and fast operation without delays.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent dynamically controls the voltage application sequence, transitioning from a static voltage charging process to a dynamic, time-controlled voltage sequence. By coordinating the substrate voltage rise with the erase signal, the system achieves precise timing without extending the overall operation time, thereby improving productivity.

Inventive Principle:

Principle #15Dynamics

3Reliability

If dummy cells are programmed after each erase operation to prevent over-erasure, then the reliability is improved, but the loss of time increases due to additional programming steps

Engineering Contradiction:

Improveover-erasure preventionVSAvoidprogramming time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The substrate is pre-charged to the first voltage level before the erase operation, which establishes the correct voltage conditions in advance. This preliminary action ensures that dummy cells are not subjected to unintended programming during the erase process, preventing over-erasure while eliminating the need for subsequent programming steps, thus saving time.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The voltage control mechanism automatically prevents over-erasure of dummy cells through self-regulating voltage application. The controlled voltage sequence inherently protects dummy cells without requiring external programming operations, making the system self-protecting and time-efficient.

Inventive Principle:

Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for precise timing of the erase operation, reduces power consumption, and saves time and power by eliminating the need for repeated charging and programming of dummy cells, resulting in improved efficiency and accuracy.

Implementation Method 1

coupling the substrate to a first voltage to increase a voltage level of the substrate

Methodology Applied

Scientific EffectVoltage application: Electric Field

Implementation Method 2

floating the control gate to make a voltage level of the control gate increase with the voltage level of the substrate

Methodology Applied

Scientific EffectVoltage coupling: Electric Field

Implementation Method 3

coupling the control gate to a second voltage via the word line to discharge charges on the isolated carrier storage layer, for erasing data

Methodology Applied

Scientific EffectCharge discharge: Electrostatic Discharge

Data Source

PatentUS7313029B2Method for erasing flash memories and related system thereof

Publication Date: 2007.12.25 SKYMEDI CORPORATION

AI summary

A method for erasing data of a flash memory is disclosed. The flash memory includes a plurality of memory cells coupled to a word line, where each of the memory cells has a substrate, an isolated carrier storage layer, and a control gate coupled to the word line. And the method includes: coupling the substrate to a first voltage to increase a voltage level of the substrate; before erasing data, floating the control gate to make a voltage level of the control gate increase with the voltage level of the substrate; and coupling the control gate to a second voltage via the word line to discharge charges on the isolated carrier storage layer for erasing data.