Flash Memory Erase Suspend Resume Control Circuit
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Solution Overview
Problem
Conventional flash memory erase operations are lengthy, causing processors in integrated circuits to delay interrupt signals and reducing system performance, as they must wait for the erase operation to complete before responding to other commands.
Innovation Solution
A memory-control circuit with a timer circuit and memory controller that suspends and resumes erase operations based on interrupt signals, allowing the erase operation to continue from a break point after the interrupt is cleared, utilizing a timer circuit with an inverter, AND gate, counter, and comparator to generate a completion signal when a predetermined count is reached.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the processor waits for the erase operation to complete before handling other commands, then the erase operation is completed correctly, but the system response time to interrupt signals is delayed
Solution Approach 1:
The patent implements dynamic control of the erase operation by introducing a suspend/resume mechanism. The erase operation can be paused when interrupt signals are received and resumed afterward, transforming a static blocking operation into a dynamic flexible one. This allows the system to balance between completing erase operations reliably and responding timely to interrupts by adjusting the operation flow based on system needs.
Solution Approach 2:
The patent uses a timer circuit to preliminarily track the erase operation progress before an interrupt occurs. By pre-calculating and monitoring the erase status in advance, the system can quickly determine whether the erase operation can be safely suspended or must be completed first, enabling faster interrupt response without compromising erase reliability.
2Reliability
If the processor delays interrupt signal handling until erase operation completion, then data erasing correctness is ensured, but integrated circuit performance is reduced
Solution Approach 1:
The patent transforms the rigid sequential execution (erase then interrupt) into a dynamic flexible flow (erase ↔ interrupt). By implementing suspend and resume functions controlled by status registers, the system can adaptively switch between completing erase operations and handling interrupts based on system priorities, thereby maintaining data erasing correctness while improving overall circuit performance.
Solution Approach 2:
The patent employs feedback mechanisms through status registers that continuously monitor erase operation progress. This feedback allows the processor to make informed decisions about whether to suspend or continue the erase operation based on interrupt requirements, enabling intelligent resource management that balances reliability and performance.
3Loss of time
If the erase operation is suspended and resumed from a break point, then the total erase time is reduced, but the control circuit complexity increases
Solution Approach 1:
The patent segments the erase operation into multiple suspendable and resumable stages by introducing break point tracking. The erase process is divided into manageable segments that can be independently paused and resumed, allowing the system to optimize timing by suspending at appropriate break points rather than forcing completion or restart, thereby reducing total erase time despite added control complexity.
Solution Approach 2:
The patent introduces status registers and control logic as intermediaries between the erase operation and the processor. These intermediaries manage the complexity of suspend/resume operations by providing standardized interfaces for tracking progress, setting break points, and controlling flow, thereby isolating the complexity from the main processor while enabling time optimization.
Data Source
AI summary
A memory-control circuit for use in an integrated circuit is provided. The memory-control circuit includes a memory controller and a timer circuit. The memory controller performs an erase operation on a target data block of the flash memory according to an erase command from a processor, and generates an erase signal. The timer circuit starts a counting operation in response to the erase signal. In response to an intellectual-property-core circuit generating an interrupt signal, the memory controller and the timer circuit respectively suspend the erase operation and the counting operation. In response to the interrupt signal being cleared, the memory controller and the timer circuit respectively resume the erase operation and the counting operation. In response to the timer circuit having counted up to a predetermined value, the timer circuit outputs a completion signal to the memory controller to indicate that the erase operation is complete.