Flash Memory Erase Verify Relaxation Prevention
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Solution Overview
Problem
Flash memory devices face challenges in ensuring complete erasure of data bits during sector-by-sector erase operations, as relaxation effects can lead to under-erased bits, and existing verify techniques may not adequately address these issues.
Innovation Solution
The proposed solution involves an erase verify method for flash memory arrays that includes performing an initial erase operation, followed by sequential verification of bits, with secondary erase pulses applied as needed to ensure all bits meet the erase criteria, and electrical stressing to accelerate relaxation effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sector-by-sector erase operations are performed on flash memory, then erase capacity and data management are improved, but relaxation effects cause under-erased bits and reduce erase completeness
Solution Approach 1:
The patent applies preliminary electrical stress to the flash memory sector before performing the erase operation. This stress phase accelerates the relaxation effect in advance, ensuring that charge trapping dielectric elements fully relax before erasure begins, thereby preventing under-erased bits while maintaining sector-by-sector erase efficiency
Solution Approach 2:
The patent implements a continuous verify process during the erase operation that repeatedly checks for under-erased bits and applies additional erase cycles as needed. This continuous verification and re-erasing ensures complete erasure despite relaxation effects, maintaining reliability while using sector-by-sector operations
2Reliability
If verify operations are performed after erase, then erase completeness is improved, but process time increases
Solution Approach 1:
The patent implements periodic verify operations at multiple stages: before erase (to establish baseline), during erase (intermediate verification), and after erase (final verification). This periodic checking approach ensures comprehensive verification while optimizing timing to minimize total process time by catching issues early rather than requiring complete re-verification
Solution Approach 2:
The patent performs a preliminary verify operation before the erase operation to establish the initial state of bits. This preliminary verification allows the system to identify bits that are already properly erased or programmed, reducing the need for extensive post-erase verification and thereby reducing total verify process time
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures that all bits in a sector are thoroughly erased, preventing under-erased states and improving the reliability of data retention by using repetitive verification and stress techniques to expedite the erase process.
Implementation Method 1
relaxation effects can lead to under-erased bits
Implementation Method 2
electrical stressing of the flash memory array, which accelerates the relaxation effect
Data Source
AI summary
Erase verify operations as described herein can be utilized for a flash memory device having an array of memory cells. The erase verify operations employ repetitive erase verify testing to double-check previously verified bits that might otherwise relax or settle into an under-erased state. Following an initial erase verify procedure, an erase verify operation may perform a secondary erase verify procedure and apply additional erase pulses to bits that have become under-erased.