Flash Memory Erase Voltage Control to Reduce Leakage Current
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Solution Overview
Problem
Conventional flash memory devices suffer from the erase disturb phenomenon, where unselected memory cells can be inadvertently erased due to leakage current during the erase operation, leading to data integrity issues.
Innovation Solution
The implementation of a flash memory device with a voltage generator that produces an erase voltage higher than ground voltage and internal voltages, which are selectively applied to both selected and unselected layers through row select circuits, reducing leakage current and minimizing the risk of erase disturb by maintaining a gate-source voltage difference that decreases the exponential function of leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ground voltage is applied to sources of select transistors during erase operation, then the erase operation can be performed, but leakage current flows through select transistors causing erase disturb in unselected memory cells
Solution Approach 1:
The patent changes the voltage parameter applied to the sources of select transistors from ground voltage (0V) to a higher voltage level (e.g., 3.3V or 5V). This parameter change reduces the gate-source voltage difference across select transistors in unselected blocks, thereby exponentially reducing leakage current and preventing erase disturb while maintaining proper erase operation in selected blocks
2Reliability
If erase voltage is applied to unselected memory blocks, then the erase operation is performed, but this causes erase disturb due to leakage current through select transistors
Solution Approach 1:
The patent introduces an intermediary voltage level (higher than ground but lower than or equal to erase voltage) that is applied to the sources of select transistors. This intermediary voltage acts as a mediator that reduces the voltage differential across select transistor gates and sources, thereby reducing leakage current and preventing unwanted erase effects in unselected blocks while allowing the erase operation to proceed in selected blocks
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces the likelihood of erase disturb by minimizing leakage current through select transistors, ensuring accurate data retention and improved operational reliability during erase operations.
Implementation Method 1
reducing leakage current and minimizing the risk of erase disturb by maintaining a gate-source voltage difference that decreases the exponential function of leakage current
Implementation Method 2
the activated row select circuit is configured to apply the erase voltage to the selected layer of the corresponding mat, and apply at least one of the erase voltage and the internal voltage to the unselected layer of the corresponding mat during an erase operation
Data Source
AI summary
A flash memory device includes; a plurality of layers, each one including memory cells arranged in a matrix of rows and columns, a layer decoder configured to select one of the plurality of layers to thereby define a selected layer and an unselected layer, a voltage generator configured to generate an erase voltage at a level higher than ground voltage, and an internal voltage, and a row select circuit configured to apply the erase voltage to the selected layer, and apply at least one of the erase voltage and the internal voltage to the unselected layer during an erase operation.