Flash Memory Erase Voltage Synchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Multi-bit flash memory devices face challenges in efficiently programming and erasing memory cells within a limited threshold voltage window, leading to variations in erase speeds among memory cells due to fabrication process variations and physical locations of word lines.
Innovation Solution
The solution involves generating and applying different word line voltages during an erase operation, with higher voltages applied to word lines connected to fast cells and lower voltages to slow cells, to reduce the electric field strength and synchronize erase speeds, thereby improving the threshold voltage distribution and erase efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a single word line voltage is applied during erase operation, then the erase operation is simple to control, but erase speed variations occur among memory cells due to fabrication process variations and physical locations
Solution Approach 1:
The patent applies different word line voltages to different word lines based on their specific characteristics (fast cells vs. slow cells). This local differentiation allows each word line to receive the optimal voltage for its erase speed, thereby achieving uniform erase performance across all memory cells while maintaining simple control logic.
2Manufacturing precision
If different word line voltages are applied to synchronize erase speeds, then erase speed uniformity is improved, but device complexity increases due to voltage generation and selection circuits
Solution Approach 1:
The patent changes the voltage parameter dynamically during the erase operation. A voltage generating unit produces different word line voltages based on the erase operation phase and word line characteristics. This parameter change approach enables erase speed synchronization without requiring complex hardware modifications, thus balancing performance improvement with device complexity.
3Manufacturing precision
If higher voltages are applied to fast cells and lower voltages to slow cells, then threshold voltage distribution is improved, but energy consumption increases
Solution Approach 1:
The patent applies partial voltage adjustments rather than maximum voltage to all word lines. Only the necessary voltage difference is applied to synchronize erase speeds, avoiding excessive energy consumption. The voltage generating unit provides just enough voltage to achieve uniform erase performance, not maximum possible voltage, thus optimizing the balance between threshold voltage distribution quality and energy efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the difference in erase speeds between fast and slow cells, enhancing the efficiency of the erase operation and improving the threshold voltage distribution, allowing for more efficient programming and erasing within a limited voltage window.
Implementation Method 1
applying a first electric field between a bulk and a first word line of the at least two word lines and applying a second electric field between the bulk and a second word line of the at least two word lines. The first electric field is different in strength from the second electric field.
Data Source
AI summary
A flash memory device includes a cell array and a voltage supplying and selecting portion. The cell array includes multiple word lines, and the voltage supplying and selecting portion is configured to generate at least two different voltages to be supplied to the word lines of the cell array during an erase operation.