Flash Memory Erase Control via Word Line Segmentation
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Solution Overview
Problem
Conventional NAND flash memory devices face challenges in achieving uniform erase speeds and threshold voltage distributions due to variations in the spacing between select lines and word lines, leading to increased erase times and potential erase failures.
Innovation Solution
A method is introduced where an electric field is applied between word lines and a substrate for a first time period, followed by maintaining this field for a portion of the word lines while reducing or removing it for the remaining word lines, with select lines floated, to control the erase process and prevent erasure of memory cells connected to specific word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional simultaneous erase method is used, then erase operation is simple, but erase speed becomes non-uniform and threshold voltage distribution widens
Solution Approach 1:
The patent segments the word lines into first word lines (adjacent to select lines) and second word lines (not adjacent to select lines). Different erase voltages are applied to different segments: a first erase voltage to first word lines and a second erase voltage to second word lines. This segmentation allows independent control of erase conditions for different cell groups, resolving the contradiction between simple operation and uniform threshold voltage distribution.
Solution Approach 2:
The patent applies local quality by differentiating erase conditions based on the spatial location of word lines relative to select lines. First word lines receive a first erase voltage while second word lines receive a second erase voltage, creating locally optimized erase conditions. This ensures that memory cells in different locations experience appropriate erase conditions, achieving uniform threshold voltage distribution across the entire memory block.
2Speed
If higher erase voltage is applied to all word lines, then erase speed increases, but threshold voltage distribution widens due to proximity to select lines
Solution Approach 1:
The patent applies local quality by differentiating erase conditions based on the spatial location of word lines relative to select lines. First word lines receive a first erase voltage while second word lines receive a second erase voltage, creating locally optimized erase conditions. This ensures that memory cells in different locations experience appropriate erase conditions, achieving uniform threshold voltage distribution across the entire memory block.
Solution Approach 2:
The patent changes the erase voltage parameter differently for different word line segments. By applying a first erase voltage to first word lines and a second erase voltage to second word lines, the patent optimizes the erase parameter for each location, preventing excessive threshold voltage widening while maintaining adequate erase speed.
3Manufacturing precision
If erase time is extended to ensure complete erase, then threshold voltage distribution improves, but productivity decreases
Solution Approach 1:
The patent segments the word lines into first word lines (adjacent to select lines) and second word lines (not adjacent to select lines). Different erase voltages are applied to different segments: a first erase voltage to first word lines and a second erase voltage to second word lines. This segmentation allows independent control of erase conditions for different cell groups, resolving the contradiction between simple operation and uniform threshold voltage distribution.
Solution Approach 2:
The patent applies preliminary action by pre-identifying which word lines are adjacent to select lines before initiating the erase operation. This allows the erase controller to pre-configulate different erase voltages for different word line segments, ensuring that cells requiring longer erase times (those near select lines) are handled appropriately without delaying the entire erase operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures consistent erase speeds across all memory cells, reduces the widening of threshold voltage distributions, and minimizes erase failures by adjusting the erase time for cells connected to word lines adjacent to select lines, thereby improving overall erase efficiency.
Implementation Method 1
simultaneously erasing memory cells in a memory block by applying an electric field between word lines and a substrate
Data Source
AI summary
In a method of erasing a non-volatile memory device an electric field is applied between a plurality of word lines and a substrate to erase memory cells in a memory block simultaneously. After a first time period elapses, the electric field applied between a first portion of the plurality of word lines and the substrate is maintained to erase memory cells, while the electric field between a second portion of the plurality of word lines and the substrate is removed or reduced.