Flash Memory Erasing Method With Self-Examining Algorithm
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Solution Overview
Problem
Conventional flash memory erasing methods are time-consuming due to the need for multiple verification and correction cycles, which can result in under-erased transistor memory cells and excessive leakage current, rendering the memory inoperative.
Innovation Solution
An erasing method with a self-examining algorithm that eliminates the do-loop between erasing and verifying processes by using flags to determine when over-erased corrections are needed, ensuring that memory sectors are correctly erased and verified without under-erased cells, and allocating fast and slow bits on separate bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple verification and correction cycles are performed to correct over-erased and under-erased transistor memory cells, then the reliability of the erasing process is improved, but the execution time of the erasing process increases significantly
Solution Approach 1:
The patent applies preliminary action by performing a pre-programming process before the main erasing operation. This pre-programming sets the initial state of memory cells to ensure they are properly prepared for erasing, which prevents the need for multiple correction cycles and reduces overall execution time while maintaining reliability
Solution Approach 2:
The patent implements feedback mechanisms through verification processes that monitor the erasing status of memory cells. By using verification results to dynamically adjust subsequent erasing operations, the system can identify and correct under-erased or over-erased cells in a single pass rather than requiring multiple iterative cycles
2Manufacturing precision
If the do-loop between erasing and verifying processes is maintained to ensure complete erasing, then the manufacturing precision of the erasing operation is improved, but the productivity of the flash memory system deteriorates
Solution Approach 1:
The patent segments the memory block into multiple memory sectors and processes them independently. This segmentation allows parallel processing of different sectors and enables the system to maintain high precision erasing for each sector while improving overall productivity by avoiding sequential processing of entire blocks
Solution Approach 2:
The patent applies partial action by performing erasing and verification on memory sectors rather than entire memory blocks. This partial processing approach maintains manufacturing precision for each sector while significantly improving productivity by reducing the total number of cells processed in each cycle
3Reliability
If over-erased correction and verification processes are performed on all transistor memory cells, then the reliability of preventing leakage current is improved, but the loss of time due to additional processing cycles increases
Solution Approach 1:
The patent applies local quality by performing over-erased correction only on specific memory sectors that are identified as needing correction, rather than processing all memory cells uniformly. This targeted approach maintains reliability by correcting leakage current issues where they actually exist while reducing overall processing time by skipping sectors that don't require correction
Data Source
AI summary
An erasing method used in a flash memory having memory blocks is illustrated, each of the memory blocks is divided into a plurality of memory sectors, and steps of the erasing method is illustrated as follows. An erasing and verifying process is performed sequentially on the memory blocks or the memory sectors of the memory block according to a memory sector enable signal. An over-erased correcting and verifying process is performed sequentially on the memory blocks or the memory sectors of the memory block according to the memory sector enable signal, wherein the memory sector enable signal is set to be asserted if an over-erased correction is performed on at least one of the memory blocks or at least one of the memory sectors of the memory block.