Flash Memory Erasure Method for Slow Bit Handling
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Solution Overview
Problem
Current flash memory erasure methods are time-consuming and unreliable due to 'slow bits' that require extended erasing times, and existing verification methods to prevent over-erasing consume excessive time and resources, especially as memory capacity increases.
Innovation Solution
The method involves setting a critical ending condition to stop simultaneous erasing of selected sectors when met, allowing for sequential erasing of remaining sectors to avoid over-erasure and reduce verification time, utilizing a threshold based on normal distribution variance to differentiate between normal and slow bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If simultaneous erasing of multiple sectors is performed to reduce erasure time, then productivity is improved, but reliability deteriorates due to slow bits requiring extended erasing times
Solution Approach 1:
The patent divides the erasure process into two distinct phases: a simultaneous multi-sector erasure phase for normal bits, and a sequential erasure phase for slow bits. This segmentation allows the system to achieve high productivity during the simultaneous phase while maintaining reliability during the sequential correction phase, resolving the contradiction between speed and reliability.
Solution Approach 2:
The patent performs preliminary verification after the simultaneous erasure to identify slow bits before proceeding to sequential erasure. This preliminary action ensures that only sectors needing additional erasure are processed sequentially, preventing redundant verification of already-erased sectors and maintaining both efficiency and reliability.
2Reliability
If verification is performed on all selected blocks to prevent over-erasing, then reliability is improved, but loss of time increases due to redundant verification
Solution Approach 1:
The patent performs verification after simultaneous erasure to identify slow bits, then uses this information to guide subsequent sequential erasure. This preliminary verification action prevents over-erasing by targeting only sectors that need it, while the sequential nature of the second phase ensures no redundant verification occurs.
Solution Approach 2:
The patent dynamically adjusts the erasure strategy based on verification results. If a sector is verified as successfully erased during simultaneous processing, the system skips sequential erasure for that sector. This dynamic adaptation eliminates redundant verification time while maintaining reliability through targeted verification and erasure.
3Reliability
If sequential erasing of sectors is performed to handle slow bits, then reliability is improved, but productivity deteriorates due to time-consuming process
Solution Approach 1:
The patent segments the erasure process into simultaneous processing for normal bits (high productivity) and sequential processing for slow bits (high reliability). By separating these two workflows, the system achieves both fast erasure of the majority of sectors and complete erasure of difficult sectors without compromising either productivity or reliability.
Solution Approach 2:
The patent applies partial sequential erasure only to sectors identified as containing slow bits, rather than sequentially erasing all sectors. This partial action approach maintains high productivity by avoiding unnecessary sequential processing of already-erased sectors while ensuring complete erasure where needed.
Data Source
AI summary
A method for erasing flash memory comprises the steps of: setting a critical ending condition; simultaneously erasing selected multiple sectors of the flash memory; stopping simultaneous erasing if one of the selected multiple sectors meets the critical ending condition; and erasing the remainder of each of the selected multiple sectors sequentially.