Flash Memory Controller Error Marking for Uncorrectable Data

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Solution Overview

Problem

Flash memory systems face challenges in accurately identifying and preventing error data from being transmitted to computer hosts, as existing error correcting mechanisms can incorrectly correct uncorrectable error bits, leading to inaccurate data being sent to the host.

Innovation Solution

A flash memory controller with a microprocessor unit, interface units, an error correcting unit, memory management unit, and a marking unit divides each page into data, redundancy, and error correcting bit areas, generating error correcting codes and recording data accuracy marks to identify and prevent the transmission of uncorrectable error data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the error correcting circuit regenerates error correcting codes based on error data, then the data can be transmitted, but the data accuracy deteriorates because uncorrectable errors are propagated

Engineering Contradiction:
Improvedata transmission capabilityVSAvoiddata accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The marking unit records data accuracy marks in advance to indicate whether data contains uncorrectable errors before transmission. This preliminary marking allows the host system to anticipate and handle potential data accuracy issues without requiring real-time error detection during transmission, thus maintaining both transmission capability and data accuracy.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system provides feedback to the host system through data accuracy marks that indicate the presence of uncorrectable errors. This feedback mechanism allows the host to adjust its data handling procedures accordingly, preventing the propagation of erroneous data while maintaining the ability to transmit data successfully.

Inventive Principle:
Principle #23Feedback

2Reliability

If the error correcting circuit executes error correcting process on all data, then data accuracy is maintained, but the processing time increases

Engineering Contradiction:
Improvedata accuracyVSAvoiderror correcting processing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system segments the data processing into two phases: during writing, the marking unit records data accuracy marks for data containing uncorrectable errors; during reading, the host system uses these marks to determine whether error correction is needed. This segmentation eliminates the need to execute the complete error correcting process on all data, significantly reducing processing time while maintaining accuracy where needed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instead of executing the full error correcting process on all data (excessive action), the system performs partial action by only applying error correction when the data accuracy marks indicate the presence of uncorrectable errors. This selective approach reduces processing time while maintaining data accuracy for affected data.

Inventive Principle:
Principle #16Partial or excessive action

3Device complexity

If the flash memory stores data without marking error status, then the storage structure is simple, but the host system cannot identify error data

Engineering Contradiction:
Improvestorage structure complexityVSAvoiderror data identification
Core Design Contradiction:
Device complexityVSDifficulty of detecting and measuring

Solution Approach 1:

The marking unit merges the error status information with the existing data storage structure by recording data accuracy marks alongside the data. This combining approach allows the host system to identify error data without requiring a completely separate error detection mechanism, thus maintaining structural simplicity while enabling effective error identification.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20100325524A1Control circuit capable of identifying error data in flash memory and storage system and method thereof
Publication Date: 2010.12.23 PHISON ELECTRONICS
  • US20100325524A1 patent drawing
  • US20100325524A1 patent drawing
  • US20100325524A1 patent drawing

AI summary

A flash memory control circuit including a microprocessor unit, a first interface unit for connecting a flash memory, a second interface unit for connecting a computer host, an error correcting unit, a memory management unit, and a marking unit is provided. The memory management unit divides each page in the flash memory into a plurality of data bit areas, and a plurality of redundancy bit areas and a plurality of error correcting bit areas corresponding to the data bit areas, wherein each of the data bit areas has a plurality of sectors for respectively storing a sector data. The marking unit stores a data accuracy mark corresponding to each sector data in the corresponding redundancy bit area to record the status of the sector data. Thereby, the flash memory controller can effectively identify error data in the flash memory by using the error correcting codes and the data accuracy marks.