Flash Memory Extra Data Error Detection and Correction
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Solution Overview
Problem
Existing flash memory systems face inefficiencies in retrieving extra data with error correction, as they either incur significant output time overhead when correcting errors for the entire row or suffer from storage inefficiencies by using separate error correcting codes for extra data.
Innovation Solution
A processing circuit and memory matrix configuration that allows for error detection and conditional error correction of extra data using shared error correction redundancy with payload data, enabling fast retrieval in error-free cases and slower retrieval when errors occur, while minimizing storage overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction is applied to the entire row including extra data, then error correction reliability is improved, but output time overhead increases significantly
Solution Approach 1:
The patent segments the error correction process into two parts: a fast error detection phase for extra data using a dedicated error detecting code, and a conditional error correction phase only when errors are detected. This segmentation allows the system to quickly identify and correct errors in extra data without unnecessarily processing the entire row, thus reducing output time overhead while maintaining correction reliability.
Solution Approach 2:
The patent applies preliminary error detection to extra data before full error correction is performed. By first checking whether errors exist in the extra data using the error detecting code, the system can determine whether to proceed with full row reading and correction, thereby avoiding unnecessary time consumption when no errors are present.
2Reliability
If a separate error correcting code is used for extra data, then error correction for extra data is enabled, but storage overhead increases
Solution Approach 1:
The patent merges the error correction resources by using the same error correcting code for both payload data and extra data. The error correcting code is applied to the combination of payload data and extra data, allowing the system to correct errors in extra data without requiring separate storage for dedicated error correction redundancy, thus avoiding additional storage overhead.
Solution Approach 2:
The patent makes the error correcting code universal by applying it to both payload data and extra data. This multi-functional approach allows a single error correcting code to serve dual purposes: correcting errors in payload data and correcting errors in extra data, thereby eliminating the need for separate error correction storage for extra data.
3Measurement precision
If the entire row is output for error correction of extra data, then correction accuracy is improved, but retrieval speed decreases
Solution Approach 1:
The patent segments the data retrieval process into two stages: first, quickly retrieve and check only the extra data using error detection; second, if errors are detected, then retrieve the entire row for correction. This segmentation maintains correction accuracy when needed while significantly improving retrieval speed for error-free cases by avoiding unnecessary full row reads.
Solution Approach 2:
The patent performs preliminary error detection on extra data before initiating full row retrieval for correction. This preliminary action allows the system to quickly identify whether correction is necessary, thereby maintaining high correction accuracy when errors exist while avoiding the time penalty of reading the entire row when no errors are present.
Data Source
AI summary
An apparatus comprises a memory with a matrix (10) with rows and columns of memory cells. A read access circuit (14, 16, 18) executes a read command to read a retrieval unit comprising data from a row of the memory cells from the matrix (10) and to output data from the retrieval unit. A processing circuit (12) coupled to the read access circuit (14, 16, 18) is configured to execute an extra read operation involving issuing the read command, receiving the extra data (24), performing error detection on only the extra data (24), using an error detecting code in which the extra data is coded, conditionally performing error correction on the data from the extra data (24) using data from the retrieval unit including the payload data (22), according to an error correcting code in which the retrieval unit is coded, if the error detection indicates an error in the extra data (24). The processing circuit (12) performs further processing using the data from the extra data (22) or the corrected extra data, dependent on whether the error detection indicates an error in the extra data (22).