Flash Memory Fail Bit Counting via Segmented Verify
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Solution Overview
Problem
Conventional flash memory devices can only verify if data has been programmed or erased, but cannot determine the number of failed bits during a program operation, limiting their efficiency in data storage and retrieval.
Innovation Solution
A flash memory device and programming method that includes a page buffer unit, a data line mux unit, and a fail bit counter unit to scan columns, count failed bits, and compare them with error correction code (ECC) allowed bits, outputting a pass or fail signal based on the comparison, thereby enhancing data programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional verify operation is used, then data programming can be completed, but the number of failed bits cannot be determined
Solution Approach 1:
The verify operation is segmented into two distinct phases: a first verify operation that performs basic verification, and a second verify operation that counts failed bits. This segmentation allows the system to first ensure basic functionality before performing the more detailed counting operation, thereby resolving the contradiction between completing programming and determining fail bit counts.
Solution Approach 2:
The first verify operation is performed as a preliminary action before the second verify operation. This preliminary verification ensures that the basic programming is complete before attempting to count failed bits, preventing information loss by establishing a foundation for accurate fail bit counting.
2Productivity
If verify operation is performed during program operation, then data storage efficiency is improved, but device complexity increases
Solution Approach 1:
The verify operation is divided into two sequential phases: a first verify operation for basic verification and a second verify operation for fail bit counting. This segmentation allows the system to perform verification during programming (improving productivity) while managing complexity by breaking down the verify operation into manageable, distinct steps.
Solution Approach 2:
The system implements feedback mechanisms where the first verify operation provides information that guides the second verify operation. This feedback approach enables efficient data storage by continuously monitoring programming status and adjusting subsequent operations accordingly, while maintaining manageable device complexity through structured feedback loops.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the detection and correction of program failures by counting and managing fail bits during data programming, improving the overall efficiency and reliability of the flash memory device.
Implementation Method 1
The NAND type flash memory device is programmed or erased by injecting or draining electrons into or out of the floating gate of the NAND type flash memory device by the Fowler-Nordheim Tunneling method.
Data Source
AI summary
A flash memory device includes a memory cell array including a plurality of memory cells, a page buffer unit including a plurality of page buffers connected to bit lines of the memory cell array, a data line mux unit connected between the page buffer unit and a data line and configured to receive verification data through a page buffer during a verify operation. The flash memory device also includes a fail bit counter unit for counting the verification data, comparing counted fail bits and the number of ECC allowed bits, and outputting a pass or fail signal of a program operation according to the comparison result.